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? freescale semiconductor, inc., 2008. all rights reserved. freescale semiconductor technical data 1 mpc8544e overview this section provides a high- level overview of mpc8544e features. figure 1 shows the major functional units within the device. 1.1 key features the following list provides an overview of the device feature set: ? high-performance 32-bit book e?enhanced core built on power architecture? technology: ? 32-kbyte l1 instruction cache and 32-kbyte l1 data cache with parity protection. caches can be locked entirely or on a per-line basis, with separate locking for instructions and data. ? signal-processing engine (spe) apu (auxiliary processing unit). provides an extensive instruction set for vector (64-bit) integer and fractional operations. these instructions use both the upper and lower words of the 64-bit gprs as they are defined by the spe apu. document number: mpc8544eec rev. 1, 06/2008 contents 1. mpc8544e overview . . . . . . . . . . . . . . . . . . . . . . . . . 1 2. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 8 3. power characteristics . . . . . . . . . . . . . . . . . . . . . . . . 13 4. input clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5. reset initialization . . . . . . . . . . . . . . . . . . . . . . . . . 18 6. ddr and ddr2 sdram . . . . . . . . . . . . . . . . . . . . . 19 7. duart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8. enhanced three-speed ethernet (etsec), mii management . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 9. ethernet management interface electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 10. local bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 11. programmable interrupt controller . . . . . . . . . . . . . 58 12. jtag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 13. i 2 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 14. gpio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 15. pci . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 16. high-speed serial interfaces (hssi) . . . . . . . . . . . . 67 17. pci express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 18. package description . . . . . . . . . . . . . . . . . . . . . . . . . 87 19. clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 20. thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 21. system design information . . . . . . . . . . . . . . . . . . 111 22. device nomenclature . . . . . . . . . . . . . . . . . . . . . . . 120 23. document revision history . . . . . . . . . . . . . . . . . . 124 mpc8544e powerquicc? iii integrated processor hardware specifications
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 2 freescale semiconductor mpc8544e overview figure 1. mpc8544e block diagram ? double-precision floating-point apu. provides an instruction set for double-precision (64-bit) floating-point instructions that use the 64-bit gprs. ? 36-bit real addressing ? embedded vector and scalar single-precision fl oating-point apus. provide an instruction set for single-precision (32-bit) floating-point instructions. ? memory management unit (mmu). especially designed for embedded applications. supports 4-kbyte?4-gbyte page sizes. ? enhanced hardware and software debug support ? performance monitor facility that is similar to , but separate from, the device performance monitor the e500 defines features that are not implemented on th is device. it also generally defines some features that this device implements more specifically. an understanding of these differences can be critical to ensure proper operations. ? 256-kbyte l2 cache/sram ? flexible configuration ? full ecc support on 64-bit boundary in both cache and sram modes ? cache mode supports instruction caching, data caching, or both. ? external masters can force data to be allo cated into the cache through programmed memory ranges or special transaction types (stashing). ? 1, 2, or 4 ways can be configured for stashing only. mpc8544e e500 core 32-kbyte d-cache 32-kbyte i-cache 256-kbyte l2 cache xor acceleration local 64-bit ddr/ddr2 sdram bus controller openpic security acceleration 32-bit gigabit ethernet pci pci dma performance monitor duart 2x i 2 c coherency module e500 express pci express pci express x1 x4/x2/x1 x4/x2/x1 sgmii
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 freescale semiconductor 3 mpc8544e overview ? eight-way set-associative cache organization (32-byte cache lines) ? supports locking entire cache or selected lines. individual line locks are set and cleared through book e instructions or by externally mastered transactions. ? global locking and flash clearing done through writes to l2 configuration registers ? instruction and data locks can be flash cleared separately. ? sram features include the following: ? i/o devices access sram regions by marking transactions as snoopable (global). ? regions can reside at any ali gned location in the memory map. ? byte-accessible ecc is protected using read-modify-write transaction accesses for smaller-than-cache-line accesses. ? address translation and mapping unit (atmu) ? eight local access windows define mapping within local 36-bit address space. ? inbound and outbound atmus map to larger external address spaces. ? three inbound windows plus a configuration window on pci and pci express ? four outbound windows plus default translation for pci and pci express ? ddr/ddr2 memory controller ? programmable timing supporting ddr and ddr2 sdram ? 64-bit data interface ? four banks of memory supported, each up to 4 gbytes, to a maximum of 16 gbytes ? dram chip configurations from 64 mbits to 4 gbits with x8/x16 data ports ? full ecc support ? page mode support ? up to 16 simultaneous open pages for ddr ? up to 32 simultaneous open pages for ddr2 ? contiguous or discontiguous memory mapping ? sleep mode support for self-refresh sdram ? on-die termination support when using ddr2 ? supports auto refreshing ? on-the-fly power management using cke signal ? registered dimm support ? fast memory access via jtag port ? 2.5-v sstl_2 compatible i/o (1.8-v sstl_1.8 for ddr2) ? programmable interrupt controller (pic) ? programming model is compliant with the openpic architecture. ? supports 16 programmable interrupt a nd processor task priority levels ? supports 12 discrete external interrupts ? supports 4 message interrupts with 32-bit messages
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 4 freescale semiconductor mpc8544e overview ? supports connection of an external interr upt controller such as the 8259 programmable interrupt controller ? four global high resolution timers/count ers that can generate interrupts ? supports a variety of other internal interrupt sources ? supports fully nested interrupt delivery ? interrupts can be routed to external pin for external processing. ? interrupts can be routed to the e500 core ?s standard or critical interrupt inputs. ? interrupt summary registers allow fast identification of interrupt source. ? integrated security engine (sec) optimized to pr ocess all the algorithms associated with ipsec, ike, wtls/wap, ssl/tls, and 3gpp ? four crypto-channels, each supporting multi-command descriptor chains ? dynamic assignment of crypto-execution units via an integrated controller ? buffer size of 256 bytes for each execution unit, with flow control for large data sizes ? pkeu?public key execution unit ? rsa and diffie-hellman; programmable field size up to 2048 bits ? elliptic curve cryptography with f 2 m and f(p) modes and programmable field size up to 511 bits ? deu?data encryption standard execution unit ? des, 3des ? two key (k1, k2, k1) or three key (k1, k2, k3) ? ecb and cbc modes for both des and 3des ? aesu?advanced encryption standard unit ? implements the rijndael symmetric key cipher ? ecb, cbc, ctr, and ccm modes ? 128-, 192-, and 256-bit key lengths ? afeu?arc four execution unit ? implements a stream cipher compatible with the rc4 algorithm ? 40- to 128-bit programmable key ? mdeu?message digest execution unit ? sha with 160- or 256-bit message digest ? md5 with 128-bit message digest ? hmac with either algorithm ? keu?kasumi execution unit ? implements f8 algorithm for encryption and f9 algorithm for integrity checking ? also supports a5/3 and gea-3 algorithms ? rng?random number generator ? xor engine for parity checking in raid storage applications ? dual i 2 c controllers
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 freescale semiconductor 5 mpc8544e overview ? two-wire interface ? multiple master support ? master or slave i 2 c mode support ? on-chip digital filtering rejects spikes on the bus ? boot sequencer ? optionally loads configuration data from serial rom at reset via the i 2 c interface ? can be used to initialize configuration registers and/or memory ? supports extended i 2 c addressing mode ? data integrity checked with preamble signature and crc ? duart ? two 4-wire interfaces (sin, sout, rts , cts ) ? programming model compatible with the original 16450 uart and the pc16550d ? local bus controller (lbc) ? multiplexed 32-bit address and data bus operating at up to 166 mhz ? eight chip selects support eight external slaves ? up to eight-beat burst transfers ? the 32-, 16-, and 8-bit port sizes are controlled by an on-chip memory controller. ? two protocol engines available on a per chip select basis: ? general-purpose chip select machine (gpcm) ? three user programmable machines (upms) ? parity support ? default boot rom chip select with configurable bus width (8, 16, or 32 bits) ? two enhanced three-speed ethernet controllers (etsecs) ? three-speed support (10/100/1000 mbps) ? two ieee standard 802.3?, 802.3u?, 802.3x?, 802.3z?, 802.3ac?, and 802.3ab? compliant controllers ? support for various ethernet physical interfaces: ? 1000 mbps full-duplex ieee 802.3 gmii, ieee 802.3z tbi, rtbi, sgmii, and rgmii. ? 10/100 mbps full- and half-duplex ieee 802.3 mii, ieee 802.3 rgmii, and rmii. ? flexible configuration for multiple phy interface configurations. ? tcp/ip acceleration and qos features available ? ip v4 and ip v6 header recognition on receive ? ip v4 header checksum verification and generation ? tcp and udp checksum verification and generation ? per-packet configurable acceleration ? recognition of vlan, stacked (queue in queue) vlan, 802.2, pppoe session, mpls stacks, and esp/ah ip-security headers
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 6 freescale semiconductor mpc8544e overview ? supported in all fifo modes ? quality of service support: ? transmission from up to eight physical queues ? reception to up to eight physical queues ? full- and half-duplex ethernet support (1000 mbps supports only full duplex): ? ieee standard 802.3 full-duplex flow contro l (automatic pause frame generation or software-programmed pause frame generation and recognition) ? programmable maximum frame length supports jumbo frames (up to 9.6 kbytes) and ieee standard 802.1? virtual local area network (vlan) tags and priority ? vlan insertion and deletion ? per-frame vlan control word or default vlan for each etsec ? extracted vlan control word passed to software separately ? retransmission following a collision ? crc generation and verification of inbound/outbound frames ? programmable ethernet preamble insertion and extraction of up to 7 bytes ? mac address recognition: ? exact match on primary and vi rtual 48-bit unicast addresses ? vrrp and hsrp support for seamless router fail-over ? up to 16 exact-match mac addresses supported ? broadcast address (accept/reject) ? hash table match on up to 512 multicast addresses ? promiscuous mode ? buffer descriptors backward compatible with mpc8260 and mpc860t 10/100 ethernet programming models ? rmon statistics support ? 10-kbyte internal transmit and 2-kbyte receive fifos ? mii management interface for control and status ? ability to force allocation of header information and buffer descriptors into l2 cache ? ocean switch fabric ? full crossbar packet switch ? reorders packets from a source based on priorities ? reorders packets to bypass blocked packets ? implements starvation avoidance algorithms ? supports packets with payloads of up to 256 bytes ? integrated dma controller ? four-channel controller ? all channels accessible by both the local and remote masters ? extended dma functions (advanced chaining and striding capability)
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 freescale semiconductor 7 mpc8544e overview ? support for scatter and gather transfers ? misaligned transfer capability ? interrupt on completed segment, link, list, and error ? supports transfers to or from any local memory or i/o port ? selectable hardware-enforced coherency (snoop/no snoop) ? ability to start and flow control each dma channel from external 3-pin interface ? ability to launch dma from single write transaction ? pci controller ? pci 2.2 compatible ? one 32-bit pci port with support for speeds from 16 to 66 mhz ? host and agent mode support ? 64-bit dual address cycle (dac) support ? supports pci-to-memory and memory-to-pci streaming ? memory prefetching of pci read accesses ? supports posting of processor-to-pci and pci-to-memory writes ? pci 3.3-v compatible ? selectable hardware-enforced coherency ? three pci express interfaces ? two x4 link width interfaces and one x1 link width interface ? pci express 1.0a compatible ? auto-detection of number of connected lanes ? selectable operation as root complex or endpoint ? both 32- and 64-bit addressing ? 256-byte maximum payload size ? virtual channel 0 only ? traffic class 0 only ? full 64-bit decode with 32-bit wide windows ? power management ? supports power saving modes: doze, nap, and sleep ? employs dynamic power management, which au tomatically minimizes power consumption of blocks when they are idle ? system performance monitor ? supports eight 32-bit counters that count the occurrence of selected events ? ability to count up to 512 counter-specific events ? supports 64 reference events that can be counted on any of the 8 counters ? supports duration and quantity threshold counting ? burstiness feature that permits counting of burst events with a programmable time between bursts
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 8 freescale semiconductor electrical characteristics ? triggering and chaining capability ? ability to generate an interrupt on overflow ? system access port ? uses jtag interface and a tap controller to access entire system memory map ? supports 32-bit accesses to configuration registers ? supports cache-line burst accesses to main memory ? supports large block (4-kbyte) uploads and downloads ? supports continuous bit streaming of en tire block for fast upload and download ? ieee 1149.1? compliant, jtag boundary scan ? 783 fc-pbga package 2 electrical characteristics this section provides the ac and dc electrical specifications and thermal characteristics for the mpc8544e. this device is currently targeted to these specifications. some of these specifications are independent of the i/o cell, but are included for a more complete reference. these are not purely i/o buffer design specifications. 2.1 overall dc electrical characteristics this section covers the ratings, conditions, and other characteristics. 2.1.1 absolute maximum ratings table 1 provides the absolute maximum ratings. table 1. absolute maximum ratings 1 characteristic symbol max value unit notes core supply voltage v dd ?0.3 to 1.1 v pll supply voltage av dd ?0.3 to 1.1 v core power supply for serdes transceivers sv dd ?0.3 to 1.1 v pad power supply for serdes transceivers xv dd ?0.3 to 1.1 v ddr and ddr2 dram i/o voltage gv dd ?0.3 to 2.75 ?0.3 to 1.98 v three-speed ethernet i/o, mii management voltage lv dd (etsec1) ?0.3 to 3.63 ?0.3 to 2.75 v tv dd (etsec3) ?0.3 to 3.63 ?0.3 to 2.75 v pci, duart, system control and power management, i 2 c, and jtag i/o voltage ov dd ?0.3 to 3.63 v
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 freescale semiconductor 9 electrical characteristics 2.1.2 recommended operating conditions table 2 provides the recommended operating conditions fo r this device. note that the values in table 2 are the recommended and tested operating conditions. proper device operation outside these conditions is not guaranteed. local bus i/o voltage bv dd ?0.3 to 3.63 ?0.3 to 2.75 ?0.3 to 1.98 v input voltage ddr/ddr2 dram signals mv in ?0.3 to (gv dd + 0.3) v 2 ddr/ddr2 dram reference mv ref ?0.3 to (gv dd + 0.3) v 2 three-speed ethernet signals lv in tv in ?0.3 to (lv dd + 0.3) ?0.3 to (tv dd + 0.3) v2 local bus signals bv in ?0.3 to (bv dd + 0.3) duart, sysclk, system control and power management, i 2 c, and jtag signals ov in ?0.3 to (ov dd + 0.3) v 2 pci ov in ?0.3 to (ov dd + 0.3) v 2 storage temperature range t stg ?55 to 150 c notes: 1. functional and tested operating conditions are given in ta b l e 2 . absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. stresses beyond those listed may affect device reliability or cause. 2. (m,l,o)v in , and mv ref may overshoot/undershoot to a voltage and for a maximum duration as shown in figure 2 . table 2. recommended operating conditions characteristic symbol recommended value unit notes core supply voltage v dd 1.0 50 mv v pll supply voltage av dd 1.0 50 mv v 1 core power supply for serdes transceivers sv dd 1.0 50 mv v pad power supply for serdes transceivers xv dd 1.0 50 mv v ddr and ddr2 dram i/o voltage gv dd 2.5 v 125 mv 1.8 v 90 mv v2 three-speed ethernet i/o voltage lv dd (etsec1) 3.3 v 165 mv 2.5 v 125 mv v4 tv dd (etsec3) 3.3 v 165 mv 2.5 v 125 mv pci, duart, pci express, system control and power management, i 2 c, and jtag i/o voltage ov dd 3.3 v 165 mv v 3 local bus i/o voltage bv dd 3.3 v 165 mv 2.5 v 125 mv 1.8 v 90 mv v5 table 1. absolute maximum ratings 1 (continued) characteristic symbol max value unit notes
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 10 freescale semiconductor electrical characteristics input voltage ddr and ddr2 dram signals mv in gnd to gv dd v2 ddr and ddr2 dram reference mv ref gnd to gv dd /2 v 2 three-speed ethernet signals lv in tv in gnd to lv dd gnd to tv dd v4 local bus signals bv in gnd to bv dd v5 pci, local bus, duart, sysclk, system control and power management, i 2 c, and jtag signals ov in gnd to ov dd v3 junction temperature range t j 0 to 105 c notes: 1. this voltage is the input to the filter discussed in section 21.2.1, ?pll power supply filtering,? and not necessarily the voltage at the av dd pin, which may be reduced from v dd by the filter. 2. caution: mv in must not exceed gv dd by more than 0.3 v. this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 3. caution: ov in must not exceed ov dd by more than 0.3 v. this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 4. caution: t/lv in must not exceed t/ lv dd by more than 0.3 v. this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 5. caution: bv in must not exceed bv dd by more than 0.3 v. this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. table 2. recommended operating conditions (continued) characteristic symbol recommended value unit notes
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 freescale semiconductor 11 electrical characteristics figure 2 shows the undershoot and overshoot voltages at the interfaces of the mpc8544e. figure 2. overshoot/undershoot voltage for gv dd /ov dd /lv dd /bv dd /tv dd the core voltage must always be provided at nominal 1.0 v (see table 2 for actual recommended core voltage). voltage to the processor interface i/os are provided through separate sets of supply pins and must be provided at the voltages shown in table 2 . the input voltage threshold scales with respect to the associated i/o supply voltage. ov dd and lv dd based receivers are simple cmos i/o circuits and satisfy appropriate lvcmos type specifications. the ddr2 sdram interface uses a single-ended differential receiver referenced the externally supplied mv ref signal (nominally set to gv dd /2) as is appropriate for the sstl2 electrical signaling standard. gnd gnd ? 0.3 v gnd ? 0.7 v not to exceed 10% b/g/l/ov dd + 20% b/g/l/ov dd b/g/l/ov dd + 5% of t clock 1 1. t clock refers to the clock period associated with the respective interface: v ih v il notes: 2. please note that with the pci overshoot allowed (as specified above), the device does not fully comply with the maximum ac ratings and device protection guideline outlined in section 4.2.2.3 of the pci 2.2 local bus specifications . for i 2 c and jtag, t clock references sysclk. for ddr, t clock references mclk. for etsec, t clock references ec_gtx_clk125. for lbiu, t clock references lclk. for pci, t clock references pci_clk or sysclk.
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 12 freescale semiconductor electrical characteristics 2.1.3 output driver characteristics table 3 provides information on the characteristics of the output driver strengths. 2.2 power sequencing the device requires its power rails to be applied in specific sequence in order to ensure proper device operation. these requirements are as follows for power up: 1. v dd , av dd _ n , bv dd , lv dd , sv dd , ov dd , tv dd , xv dd 2. gv dd note that all supplies must be at their stable values within 50 ms. items on the same line have no ordering requirement w ith respect to one another. items on separate lines must be ordered sequentially such that voltage rails on a previous step must reach 90% of their value before the voltage rails on the current step reach 10% of theirs. in order to guarantee mcke low during power-up, the above sequencing for gv dd is required. if there is no concern about any of the ddr signals being in an indeterminate state during power up, then the sequencing for gv dd is not required. from a system standpoint, if any of the i/o power supplies ramp prior to the v dd core supply, the i/os associated with that i/o supply may drive a logic one or zero during power-up, and extra current may be drawn by the device. table 3. output drive capability driver type programmable output impedance ( ) supply vo l ta g e notes local bus interface utilities signals 25 35 bv dd = 3.3 v bv dd = 2.5 v 1 45 (default) 45 (default) 125 bv dd = 3.3 v bv dd = 2.5 v bv dd = 1.8 v pci signals 25 ov dd = 3.3 v 2 42 (default) ddr signal 20 gv dd = 2.5 v ddr2 signal 16 32 (half strength mode) gv dd = 1.8 v tsec signals 42 lv dd = 2.5/3.3 v duart, system control, jtag 42 ov dd = 3.3 v i 2 c 150 ov dd = 3.3 v notes: 1. the drive strength of the local bus interface is determined by the configuration of the appropriate bits in porimpscr. 2. the drive strength of the pci interface is determined by the setting of the pci_gnt1 signal at reset.
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 freescale semiconductor 13 power characteristics 3 power characteristics the estimated typical core power dissipation for the core complex bus (ccb) versus the core frequency for this family of powerquicc iii devices is shown in table 4 . because i/o usage varies from design to design, power dissipation estimates for the i/o supplies are provided in table 5 . table 4. mpc8544 core power dissipation power mode core frequency (mhz) platform frequency (mhz) v dd (v) junction temperature ( c) power (w) notes typical 667 333 1.0 65 2.6 1, 2 thermal 105 4.5 1, 3 maximum 7.15 1, 4 typical 800 400 1.0 65 2.9 1, 2 thermal 105 4.8 1, 3 maximum 7.35 1, 4 typical 1000 400 1.0 65 3.6 1, 2 thermal 105 5.3 1, 3 maximum 7.5 1, 4 notes: 1. these values specify the power consumption at nominal voltage and apply to all valid processor bus frequencies and configurations. the values do not include power dissipation for i/o supplies. 2. typical power is an average value measured at the nominal recommended core voltage (v dd ) and 65 c junction temperature (see ta b l e 2 ) while running the dhrystone 2.1 benchmark. 3. thermal power is the average power measured at nominal core voltage (v dd ) and maximum operating junction temperature (see ta b l e 2 ) while running the dhrystone 2.1 benchmark. 4. maximum power is the maximum power measured at nominal core voltage (v dd ) and maximum operating junction temperature (see ta b l e 2 ) while running a smoke test which includes an entirely l1-cache-resident, contrived sequence of instructions which keep the execution unit maximally busy. table 5. mpc8544e estimated i/o power dissipation interface parameters 1.0 v (xv dd ) 1.8 v (gv dd ) 2.5 v (b/g/lv dd ) 3.3 v (b/l/ov dd ) comments ddr 333 mhz data 0.38 w 0.73 w 400 mhz data 0.46 w 533 mhz data 0.60 w pci express x4, 2.5 g-baud 0.36 w pci 32-bit, 66 mhz 0.07 w power per pci port 32-bit, 33 mhz 0.04 w
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 14 freescale semiconductor power characteristics local bus 32-bit, 133 mhz 0.14 w 0.24 w 32-bit, 66 mhz 0.07 w 0.13 w 32-bit, 33 mhz 0.04 w 0.07 w etsec (10/100/1000 ethernet) mii 0.01 w power per etsec used gmii 0.07 w tbi 0.07 w rgmii 0.04 w rtbi 0.04 w etsec (packet fifo) 8-bit, 200 mhz 0.11 w power per fifo interface used 8-bit, 155 mhz 0.08 w table 5. mpc8544e estimated i/o power dissipation (continued) interface parameters 1.0 v (xv dd ) 1.8 v (gv dd ) 2.5 v (b/g/lv dd ) 3.3 v (b/l/ov dd ) comments
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 freescale semiconductor 15 input clocks 4 input clocks 4.1 system clock timing table 6 provides the system clock (sysclk) ac timing specifications for the mpc8544e. 4.1.1 sysclk and spread spectrum sources spread spectrum clock sources are an increasingly popular way to control electromagnetic interference emissions (emi) by spreading the emitted noise to a wider spectrum and reducing the peak noise magnitude in order to meet industry and government requirements. these clock sources intentionally add long-term jitter in order to diffuse the emi spectral content. the jitter specification given in table 6 considers short-term (cycle-to-cycle) jitter only and the clock generator?s cycle-to-cycle output jitter should meet the mpc8544e input cycle-to-cycle jitter requirement. frequency modulation and spread are separate concerns, and the mpc8544e is compatible with spread spectrum sources if the recommendations listed in table 7 are observed. table 6. sysclk ac timing specifications at recommended operating conditions (see table 2 ) with ov dd = 3.3 v 165 mv. parameter/condition symbol min typical max unit notes sysclk frequency f sysclk 33 ? 133 mhz 1 sysclk cycle time t sysclk 7.5 ? 30.3 ns ? sysclk rise and fall time t kh , t kl 0.6 1.0 2.1 ns 2 sysclk duty cycle t khk /t sysclk 40 ? 60 % ? sysclk jitter ? ? ? 150 ps 3, 4 notes: 1. caution: the ccb clock to sysclk ratio and e500 core to ccb clock ratio settings must be chosen such that the resulting sysclk frequency, e500 (core) frequency, and ccb clock frequency do not exceed their respective maximum or minimum operating frequencies. refer to section 19.2, ?ccb/sysclk pll ratio,? and section 19.3, ?e500 core pll ratio,? for ratio settings. 2. rise and fall times for sysclk are measured at 0.6 and 2.7 v. 3. this represents the total input jitter?short- and long-term. 4. the sysclk driver?s closed loop jitter bandwidth should be <500 khz at ?20 db. the bandwidth must be set low to allow cascade-connected pll-based devices to track sysclk drivers with the specified jitter.
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 16 freescale semiconductor input clocks it is imperative to note that the processor?s minimum and maximum sysclk, core, and vco frequencies must not be exceeded regardless of the type of clock source. therefore, systems in which the processor is operated at its maximum rated e 500 core frequency should avoid violating the stated limits by using down-spreading only. 4.2 real-time clock timing the rtc input is sampled by the platform clock (ccb clock). the output of the sampling latch is then used as an input to the counters of the pic and the timebase unit of the e500. there is no jitter specification. the minimum pulse width of the rtc signal should be greater than 2 the period of the ccb clock. that is, minimum clock high time is 2 t ccb , and minimum clock low time is 2 t ccb . there is no minimum rtc frequency; rtc may be grounded if not needed. 4.3 etsec gigabit reference clock timing table 8 provides the etsec gigabit reference clocks (ec_gtx_clk125) ac timing specifications for the mpc8544e. table 7. spread spectrum clock source recommendations at recommended operating conditions. see ta b l e 2 . parameter min max unit notes frequency modulation 20 60 khz frequency spread 0 1.0 % 1 note: 1. sysclk frequencies resulting from frequency spreading, and the resulting core and vco frequencies, must meet the minimum and maximum specifications given in table 6 . table 8. ec_gtx_clk125 ac timing specifications parameter/condition symbol min typical max unit notes ec_gtx_clk125 frequency f g125 ?125?mhz ec_gtx_clk125 cycle time t g125 ?8?ns ec_gtx_clk rise and fall time lv dd , tv dd = 2.5 v lv dd , tv dd = 3.3 v t g125r /t g125f ?? 0.75 1.0 ns 1 ec_gtx_clk125 duty cycle gmii, tbi 1000base-t for rgmii, rtbi t g125h /t g125 45 47 ? 55 53 %2 notes: 1. rise and fall times for ec_gtx_clk125 are measured from 0.5 and 2.0 v for l/tv dd = 2.5 v, and from 0.6 and 2.7 v for l/tvdd = 3.3 v. 2. ec_gtx_clk125 is used to generate the gtx clock for t he etsec transmitter with 2% degradation. ec_gtx_clk125 duty cycle can be loosened from 47%/53% as long as the phy device can tolerate the duty cycle generated by the etsec gtx_clk. see section 8.7.4, ?rgmii and rtbi ac timing specifications,? for duty cycle for 10base-t and 100base-t reference clock.
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 freescale semiconductor 17 input clocks 4.4 platform to fifo restrictions please note the following fifo maximum speed restrictions based on platform speed. for fifo gmii mode: fifo tx/rx clock frequency <= platform clock frequency/4.2 for example, if the platform frequency is 533 mhz, the fifo tx/rx clock frequency should be no more than 127 mhz. for fifo encoded mode: fifo tx/rx clock frequency <= platform clock frequency/3.2 for example, if the platform frequency is 533 mhz, the fifo tx/rx clock frequency should be no more than 167 mhz. 4.5 other input clocks for information on the input clocks of other functional blocks of the platform such as serdes, and etsec, see the specific section of this document.
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 18 freescale semiconductor reset initialization 5 reset initialization this section describes the ac electrical specifications for the reset initialization timing requirements of the mpc8544e. table 9 provides the reset initialization ac timing specifications for the ddr sdram component(s). table 10 provides the pll lock times. table 9. reset initialization timing specifications 1 parameter/condition min max unit notes required assertion time of hrest 100 ? s minimum assertion time for sreset 3 ? sysclks 1 pll input setup time with stable sysclk before hreset negation 100 ? s input setup time for por configs (other than pll config) with respect to negation of hreset 4 ? sysclks 1 input hold time for all por configs (including pll config) with respect to negation of hreset 2 ? sysclks 1 maximum valid-to-high impedance time for actively driven por configs with respect to negation of hreset ? 5 sysclks 1 note: 1. sysclk is the primary clock input for the mpc8544e. table 10. pll lock times parameter/condition min max unit notes core and platform pll lock times ? 100 s local bus pll ? 50 s pci bus lock time ? 50 s
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 freescale semiconductor 19 ddr and ddr2 sdram 6 ddr and ddr2 sdram this section describes the dc and ac electrical specifications for the ddr sdram interface of the mpc8544e. note that ddr sdram is gv dd (typ) = 2.5 v and ddr2 sdram is gv dd (typ) = 1.8 v. 6.1 ddr sdram dc electrical characteristics table 11 provides the recommended operating conditions for the ddr sdram component(s) of the mpc8544e when gv dd (typ) = 1.8 v . table 12 provides the ddr2 i/o capacitance when gv dd (typ) = 1.8 v. table 11. ddr2 sdram dc electrical characteristics for gv dd (typ) = 1.8 v parameter/condition symbol min max unit notes i/o supply voltage gv dd 1.71 1.89 v 1 i/o reference voltage mv ref 0.49 gv dd 0.51 gv dd v2 i/o termination voltage v tt mv ref ? 0.04 mv ref + 0.04 v 3 input high voltage v ih mv ref + 0.26 gv dd + 0.3 v input low voltage v il ?0.3 mv ref ? 0.24 v output leakage current i oz ?50 50 a4 output high current (v out = 1.26 v) i oh ?13.4 ? ma output low current (v out = 0.33 v) i ol 13.4 ? ma notes: 1. gv dd is expected to be within 50 mv of the dram gv dd at all times. 2. mv ref is expected to be equal to 0.5 gv dd , and to track gv dd dc variations as measured at the receiver. peak-to-peak noise on mv ref may not exceed 2% of the dc value. 3. v tt is not applied directly to the device. it is the supply to which far end signal termination is made and is expected to be equal to mv ref . this rail should track variations in the dc level of mv ref . 4. output leakage is measured with all outputs disabled, 0 v v out gv dd . table 12. ddr2 sdram capacitance for gv dd (typ) = 1.8 v parameter/condition symbol min max unit notes input/output capacitance: dq, dqs, dqs c io 68pf1 delta input/output capacitance: dq, dqs, dqs c dio ?0.5pf1 note: 1. this parameter is sampled. gv dd = 1.8 v 0.090 v, f = 1 mhz, t a = 25c, v out = gv dd /2, v out (peak-to-peak) = 0.2 v.
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 20 freescale semiconductor ddr and ddr2 sdram table 13 provides the recommended operating conditions for the ddr sdram component(s) when gv dd (typ) = 2.5 v . table 14 provides the ddr i/o capacitance when gv dd (typ) = 2.5 v. table 15 provides the current draw characteristics for mv ref . table 13. ddr sdram dc electrical characteristics for gv dd (typ) = 2.5 v parameter/condition symbol min max unit notes i/o supply voltage gv dd 2.375 2.625 v 1 i/o reference voltage mv ref 0.49 gv dd 0.51 gv dd v2 i/o termination voltage v tt mv ref ? 0.04 mv ref + 0.04 v 3 input high voltage v ih mv ref + 0.31 gv dd + 0.3 v input low voltage v il ?0.3 mv ref ? 0.3 v output leakage current i oz ?50 50 a4 output high current (v out = 1.8 v) i oh ?16.2 ? ma output low current (v out = 0.42 v) i ol 16.2 ? ma notes: 1. gv dd is expected to be within 50 mv of the dram gv dd at all times. 2. mv ref is expected to be equal to 0.5 gv dd , and to track gv dd dc variations as measured at the receiver. peak-to-peak noise on mv ref may not exceed 2% of the dc value. 3. v tt is not applied directly to the device. it is the supply to which far end signal termination is made and is expected to be equal to mv ref . this rail should track variations in the dc level of mv ref . 4. output leakage is measured with all outputs disabled, 0 v v out gv dd . table 14. ddr sdram capacitance for gv dd (typ) = 2.5 v parameter/condition symbol min max unit notes input/output capacitance: dq, dqs c io 68pf1 delta input/output capacitance: dq, dqs c dio ?0.5pf1 note: 1. this parameter is sampled. gv dd = 2.5 v 0.125 v, f = 1 mhz, t a =25c, v out = gv dd /2, v out (peak-to-peak) = 0.2 v. table 15. current draw characteristics for mv ref parameter/condition symbol min max unit notes current draw for mv ref i mvref ? 500 a1 note: 1. the voltage regulator for mv ref must be able to supply up to 500 a current.
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 freescale semiconductor 21 ddr and ddr2 sdram 6.2 ddr sdram ac electrical characteristics this section provides the ac electrical characteristics for the ddr sdram interface. 6.2.1 ddr sdram input ac timing specifications table 16 provides the input ac timing specifications for the ddr sdram when gv dd (typ) = 1.8 v. table 17 provides the input ac timing specifications for the ddr sdram when gv dd (typ) = 2.5 v. table 18 provides the input ac timing specifications for the ddr sdram interface. table 16. ddr2 sdram input ac timing specifications for 1.8-v interface at recommended operating conditions. parameter symbol min max unit notes ac input low voltage v il ?mv ref ? 0.25 v ac input high voltage v ih mv ref + 0.25 ? v table 17. ddr sdram input ac timing specifications for 2.5-v interface at recommended operating conditions. parameter symbol min max unit notes ac input low voltage v il ?mv ref ? 0.31 v ac input high voltage v ih mv ref + 0.31 ? v table 18. ddr sdram input ac timing specifications at recommended operating conditions. parameter symbol min max unit notes controller skew for mdqs?mdq/mecc/mdm t ciskew ps 1, 2 533 mhz ?300 300 3 400 mhz ?365 365 333 mhz ?390 390 notes: 1. t ciskew represents the total amount of skew consumed by the controller between mdqs[n] and any corresponding bit that will be captured with mdqs[n]. this should be subtracted from the total timing budget. 2. the amount of skew that can be tolerated from mdqs to a corresponding mdq signal is called t diskew . this can be determined by the following equation: t diskew = (t/4 ? abs(t ciskew )), where t is the clock period and abs(t ciskew ) is the absolute value of t ciskew . see figure 3 . 3. maximum ddr1 frequency is 400 mhz.
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 22 freescale semiconductor ddr and ddr2 sdram figure 3. ddr sdram input timing diagram (t diskew ) 6.2.2 ddr sdram output ac timing specifications table 19. ddr sdram output ac timing specifications at recommended operating conditions. parameter symbol 1 min max unit notes mck[n] cycle time, mck[n]/mck [n] crossing t mck 3.75 6 ns 2 addr/cmd output setup with respect to mck t ddkhas ns 3 533 mhz 400 mhz 333 mhz 1.48 1.95 2.40 ? ? ? 7 addr/cmd output hold with respect to mck t ddkhax ns 3 533 mhz 400 mhz 333 mhz 1.48 1.95 2.40 ? ? ? 7 mcs [n] output setup with respect to mck t ddkhcs ns 3 533 mhz 400 mhz 333 mhz 1.48 1.95 2.40 ? ? ? 7 mcs [n] output hold with respect to mck t ddkhcx ns 3 533 mhz 400 mhz 333 mhz 1.48 1.95 2.40 ? ? ? 7 mck to mdqs skew t ddkhmh ?0.6 0.6 ns 4 mck [n] mck[n] t mck mdq[x] mdqs[n] d1 d0 t diskew t diskew
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 freescale semiconductor 23 ddr and ddr2 sdram note for the addr/cmd setup and hold specifications in table 19 , it is assumed that the clock control register is set to adjust the memory clocks by 1/2 applied cycle. mdq/mecc/mdm output setup with respect to mdqs t ddkhds, t ddklds ps 5 533 mhz 400 mhz 333 mhz 538 700 900 ? ? ? 7 mdq/mecc/mdm output hold with respect to mdqs t ddkhdx, t ddkldx ps 5 533 mhz 400 mhz 333 mhz 538 700 900 ? ? ? 7 mdqs preamble start t ddkhmp ?0.5 t mck ? 0.6 ?0.5 t mck + 0.6 ns 6 mdqs epilogue end t ddkhme ?0.6 0.6 ns 6 notes: 1. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. output hold time can be read as ddr timing (dd) from the rising or falling edge of the reference clock (kh or kl) until the output went invalid (ax or dx). for example, t ddkhas symbolizes ddr timing (dd) for the time t mck memory clock reference (k) goes from the high (h) state until outputs (a) are setup (s) or output valid time. also, t ddkldx symbolizes ddr timing (dd) for the time t mck memory clock reference (k) goes low (l) until data outputs (d) are invalid (x) or data output hold time. 2. all mck/mck referenced measurements are made from the crossing of the two signals 0.1 v. 3. addr/cmd includes all ddr sdram output signals except mck/mck , mcs , and mdq/mecc/mdm/mdqs. 4. note that t ddkhmh follows the symbol conventions described in note 1. for example, t ddkhmh describes the ddr timing (dd) from the rising edge of the mck[n] clock (kh) until the mdqs signal is valid (mh). t ddkhmh can be modified through control of the dqss override bits in the timing_cfg_2 register. this will typically be set to the same delay as the clock adjust in the clk_cntl register. the timing parameters listed in the table assume that these two parameters have been set to the same adjustment value. see the mpc8544e powerquicc iii integrated communications processor reference manual, for a description and understanding of the timing modifications enabled by use of these bits. 5. determined by maximum possible skew between a data strobe (mdqs) and any corresponding bit of data (mdq), ecc (mecc), or data mask (mdm). the data strobe should be centered inside of the data eye at the pins of the microprocessor. 6. all outputs are referenced to the rising edge of mck[n] at the pins of the microprocessor. note that t ddkhmp follows the symbol conventions described in note 1. 7. maximum ddr1 frequency is 400 mhz. table 19. ddr sdram output ac timing specifications (continued) at recommended operating conditions. parameter symbol 1 min max unit notes
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 24 freescale semiconductor ddr and ddr2 sdram figure 4 shows the ddr sdram output timing for the mck to mdqs skew measurement (t ddkhmh ). figure 4. timing diagram for t ddkhmh figure 5 shows the ddr sdram output timing diagram. figure 5. ddr sdram output timing diagram mdqs mck [n] mck[n] t mck mdqs t ddkhmh (max) = 0.6 ns t ddkhmh (min) = ?0.6 ns addr/cmd t ddkhas , t ddkhcs t ddkhmh t ddklds t ddkhds mdq[x] mdqs[n] mck [n] mck[n] t mck t ddkldx t ddkhdx d1 d0 t ddkhax , t ddkhcx write a0 noop t ddkhme t ddkhmp
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 freescale semiconductor 25 duart figure 6 provides the ac test load for the ddr bus. figure 6. ddr ac test load 7duart this section describes the dc and ac electri cal specifications for the duart interface of the mpc8544e. 7.1 duart dc electrical characteristics table 20 provides the dc electrical characteristics for the duart interface. 7.2 duart ac electrical specifications table 21 provides the ac timing parameters for the duart interface. table 20. duart dc electrical characteristics parameter symbol min max unit notes high-level input voltage v ih 2ov dd + 0.3 v low-level input voltage v il ?0.3 0.8 v input current (v in = 0 v or v in = v dd )i in ?5 a1 high-level output voltage (ov dd = min, i oh = ?2 ma) v oh 2.4 ? v low-level output voltage (ov dd = min, i ol = 2 ma) v ol ?0.4v note: 1. note that the symbol v in , in this case, represents the ov in symbol referenced in ta b l e 1 and ta b l e 2 . table 21. duart ac timing specifications parameter value unit notes minimum baud rate ccb clock/1,048,576 baud 1 maximum baud rate ccb clock/16 baud 2 oversample rate 16 ? 3 notes: 1. ccb clock refers to the platform clock. 2. actual attainable baud rate will be limited by the latency of interrupt processing. 3. the middle of a start bit is detected as the eighth sampled 0 after the 1-to-0 transition of the start bit. subsequent bit va lues are sampled each sixteenth sample. output z 0 = 50 gv dd /2 r l = 50
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 26 freescale semiconductor enhanced three-speed ethernet (etsec), mii management 8 enhanced three-speed ethernet (etsec), mii management this section provides the ac and dc electrical characteristics for enhanced three-speed and mii management. 8.1 enhanced three-speed ethernet controller (etsec) (10/100/1000 mbps)?sgmii/gmii/mii/tbi/rgmii/rtbi/rmii/fifo electrical characteristics the electrical characteristics specified here apply to all gigabit media independent interface (gmii), 8-bit fifo interface (fifo), serial gigabit media independent interf ace (sgmii), media independent interface (mii), ten-bit interface (tbi), reduced gigabit media independent interface (rgmii), reduced ten-bit interface (rtbi), and reduced media independent interface (rmii) signals except management data input/output (mdio) and management data clock (mdc). the 8-bit fifo interface can operate at 3.3 or 2.5 v. the rgmii and rtbi interfaces are defined for 2.5 v, while the mii, gmii, tbi, and rmii interfaces can be operated at 3.3 or 2.5 v. whether the gmii, mii, or tbi interface is operated at 3.3 or 2.5 v, the timing is compliant with the ieee 802.3 standard. the rgmii and rtbi interfaces follow the reduced gigabit media-independent interface (rgmii) specification version 1.3 (12/10/2000). the rmii interface follows the rmii consortium rmii specification version 1.2 (3/20/1998). the sgmii interfaces follow the serial gigabit media-independent interf ace (sgmii) specification version 1.8 . the electrical characteristics for mdio and mdc are specified in section 9, ?ethernet management interface electrical characteristics.? 8.2 etsec dc electrical characteristics all gmii, mii, tbi, rgmii, rtbi, rmii, and fifo drivers and receivers comply with the dc parametric attributes specified in table 22 and table 23 . the potential applied to the input of a gmii, mii, tbi, rgmii, rtbi, rmii, and fifo receiver may exceed the potential of the receiver?s power supply (that is, a gmii driver powered from a 3.6-v supply driving v oh into a gmii receiver powered from a 2.5-v supply). tolerance for dissimilar gmii driver and receiver supply potentials is implicit in these specifications. the rgmii and rtbi signals are base d on a 2.5-v cmos interface voltage as defined by jedec eia/jesd8-5. table 22. gmii, mii, tbi, rmii and fifo dc electrical characteristics parameter symbol min max unit notes supply voltage 3.3 v lv dd tv dd 3.135 3.465 v 1, 2 output high voltage (lv dd /tv dd = min, i oh = ?4.0 ma) v oh 2.4 ? v output low voltage (lv dd /tv dd = min, i ol = 4.0 ma) v ol ? 0.5 v input high voltage v ih 1.95 ? v input low voltage v il ?0.90v input high current (v in = lv dd , v in = tv dd )i ih ?40 a 1, 2, 3
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 freescale semiconductor 27 enhanced three-speed ethernet (etsec), mii management 8.3 sgmii interface electrical characteristics each sgmii port features a 4-wire ac-coupled serial link from the dedicated serdes 2 interface of mpc8544e as shown in figure 7 , where c tx is the external (on board) ac-coupled capacitor. each output pin of the serdes transmitter differential pair features 50- output impedance. each input of the serdes receiver differential pair features 50- on-die termination to sgnd_srds2 (xcorevss). the reference circuit of the serdes transmitter and receiver is shown in figure 7 . when an etsec port is configured to operate in sgmii mode, the parallel interface?s output signals of this etsec port can be left floating. the input si gnals should be terminated based on the guidelines described in section 21.5, ?connection recommendations,? as long as such termination does not violate the desired por configuration require ment on these pins, if applicable. when operating in sgmii mode, the etsec ec_gtx_clk125 clock is not required for this port. instead, serdes reference clock is required on sd2_ref_clk and sd2_ref_clk pins. 8.3.1 ac requirements for sgmii sd2_ref_clk and sd2_ref_clk table 24 lists the sgmii serdes reference clock ac requirements. please note that sd2_ref_clk and sd2_ref_clk are not intended to be used with, and shoul d not be clocked by, a spread spectrum clock source. input low current (v in = gnd) i il ?600 ? a3 notes: 1. lv dd supports etsec1. 2. tv dd supports etsec3. 3. the symbol v in , in this case, represents the lv in and tv in symbols referenced in ta b l e 1 and ta b l e 2 . table 23. gmii, mii, rmii, rgmii, rtbi, tbi, and fifo dc electrical characteristics parameters symbol min max unit notes supply voltage 2.5 v lv dd /tv dd 2.375 2.625 v 1, 2 output high voltage (lv dd /tv dd = min, i oh = ?1.0 ma) v oh 2.0 ? v output low voltage (lv dd /tv dd = min, i ol = 1.0 ma) v ol ?0.4v input high voltage v ih 1.70 ? v input low voltage v il ?0.7v input current (v in = 0, v in = lv dd , v in = tv dd )i in ?15 a 1, 2, 3 notes: 1. lv dd supports etsec1. 2. tv dd supports etsec3. 3. the symbol v in , in this case, represents the lv in and tv in symbols referenced in ta b l e 1 and ta b l e 2 . table 22. gmii, mii, tbi, rmii and fifo dc electrical characteristics (continued) parameter symbol min max unit notes
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 28 freescale semiconductor enhanced three-speed ethernet (etsec), mii management 8.3.2 sgmii transmitter and receiver dc electrical characteristics table 25 and table 26 describe the sgmii serdes transmitter and receiver ac-coupled dc electrical characteristics. transmitter dc characteristics are measured at the transmitte r outputs (sd2_tx[n] and sd2_tx [n]) as depicted in figure 8 . table 24. sd2_ref_clk and sd2_ref_clk ac requirements symbol parameter description min typical max units notes t ref refclk cycle time ? 10 (8) ? ns 1 t refcj refclk cycle-to-cycle jitter. difference in the period of any two adjacent refclk cycles ??100ps t refpj phase jitter. deviation in edge location with respect to mean edge location ?50 ? 50 ps note: 1. 8 ns applies only when 125 mhz serdes2 reference clock frequency is selected via cfg_srds_sgmii_refclk during por. table 25. dc transmitter electrical characteristics parameter symbol min typ max unit notes supply voltage v dd_srds2 0.95 1.0 1.05 v output high voltage v oh ??v os -max + |v od | ?max /2 mv 1 output low voltage v ol v os -min ?|v od | -max /2 ? ? mv output ringing v ring ?? 10% output differential voltage 2,3,5 |v od | 323 500 725 mv equalization setting: 1.0x 296 459 665 equalization setting: 1.09x 269 417 604 equalization setting: 1.2x 243 376 545 equalization setting: 1.33x 215 333 483 equalization setting: 1.5x 189 292 424 equalization setting: 1.71x 162 250 362 equalization setting: 2.0x output offset voltage v os 425 500 577.5 mv 1, 4 output impedance (single ended) r o 40 60 mismatch in a pair r o ?10%
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 freescale semiconductor 29 enhanced three-speed ethernet (etsec), mii management figure 7. 4-wire ac-coupled sgmii serial link connection example change in v od between 0 and 1 |v od |? 25mv change in v os between 0 and 1 v os ?25mv output current on short to gnd i sa , i sb ?40ma notes: 1. this will not align to dc-coupled sgmii. 2. |v od | = |v sd2_txn ? v sd2_tx n |. |v od | is also referred as output differential peak voltage. v tx-diffp-p = 2*|v od | . 3. the |v od | value shown in the table assumes the following transmit equalization setting in the xmiteq cd (for serdes 2 lane 2 and 3) bit field of mpc8544e serdes 2 control register 1: ? the msbit (bit 0) of the above bit field is set to zero (selecting the full v dd-diff-p-p amplitude?power up default); ? the lsbits (bit [1:3]) of the above bit field is set based on the equalization setting shown in this table. 4. v os is also referred to as output common mode voltage. 5. the |v od | value shown in the typ column is based on the condition of xv dd_srds2-typ = 1.0 v, no common mode offset variation (v os = 500 mv), serdes2 transmitter is terminated with 100- differential load between sd2_tx[n] and sd2_tx[n]. table 25. dc transmitter electrical characteristics (continued) parameter symbol min typ max unit notes mpc8544e sgmii serdes interface 50 50 transmitter sd2_txn sd_rxm sd2_tx n sd_rx m receiver c tx c tx 50 50 sd2_rxn sd2_rx n receiver transmitter sd_txm sd_tx m c tx c tx 50 50 50 50
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 30 freescale semiconductor enhanced three-speed ethernet (etsec), mii management figure 8. sgmii transmitter dc measurement circuit 8.4 sgmii ac timing specifications this section describes the sgmii transmit and receive ac timing specifications. transmitter and receiver characteristics are measured at the transmitter outputs (sd2_tx[n] and sd2_tx [n]) or at the receiver inputs (sd2_rx[n] and sd2_rx [n]) as depicted in figure 10 , respectively. table 26. dc receiver electrical characteristics parameter symbol min typ max unit notes supply voltage v dd_srds2 0.9 1.0 1.05 v dc input voltage range ? ? ? 1 input differential voltage lsts = 0 v rx_diffpp 100 ? 1200 mv 2, 4 lsts = 1 175 ? loss of signal threshold lsts = 0 vl os 30 ? 100 mv 3, 4 lsts = 1 65 ? 175 input ac common mode voltage v cm_acpp ??100mv5. receiver differential input impedance zrx_diff 80 ? 120 receiver common mode input impedance zrx_cm 20 ? 35 common mode input voltage vcm xcorevss ? xcorevss v 6 notes: 1. input must be externally ac-coupled. 2. v rx_diffp-p is also referred to as peak-to-peak input differential voltage 3. the concept of this parameter is equivalent to the electrical idle detect threshold parameter in pci express. refer to section 17.4.3, ?differential receiver (rx) input specifications,? for further explanation. 4. the lsts shown in this table refers to the lsts cd bit field of mpc8544e serdes 2 control register 1. 5. v cm_acp-p is also referred to as peak-to-peak ac common mode voltage. 6. on-chip termination to sgnd_srds2 (xcorevss). 50 transmitter sd2_txn sd2_tx n 50 v os v od mpc8544e sgmii serdes interface 50 50
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 freescale semiconductor 31 enhanced three-speed ethernet (etsec), mii management 8.4.1 sgmii transmit ac timing specifications table 31 provides the sgmii transmit ac timing targets. a source synchronous clock is not provided. 8.4.2 sgmii receive ac timing specifications table 32 provides the sgmii receive ac timing specifications. source synchronous clocking is not supported. clock is recovered from the data. figure 15 shows the sgmii receiver input compliance mask eye diagram. table 27. sgmii transmit ac timing specifications at recommended operating conditions with xvdd_srds2 = 1.0 v 5%. parameter symbol min typ max unit notes deterministic jitter j d ? ? 0.17 ui p-p tot a l j itt e r j t ? ? 0.35 ui p-p unit interval u i 799.92 800 800.08 ps 2 v od fall time (80%?20%) t fall 50 ? 120 ps v od rise time (20%?80%) t rise 50 ? 120 ps notes; 1. source synchronous clock is not supported. 2. each ui value is 800 ps 100 ppm. table 28. sgmii receiver ac timing specifications at recommended operating conditions with xvdd_srds2 = 1.0 v 5%. parameter symbol min typ max unit notes deterministic jitter tolerance j d 0.37 ? ? ui p-p 1 combined deterministic and random jitter tolerance j dr 0.55 ? ? ui p-p 1 sinusoidal jitter tolerance jsin 0.1 ? ? ui p-p 1 total jitter tolerance j t 0.65 ? ? ui p-p 1 bit error ratio ber ? ? 10 -12 unit interval ui 799.92 800 800.08 ps 2 ac coupling capacitor c tx 5?200nf3 notes: 1. measured at receiver. 2. each ui value is 800 ps 100 ppm. 3. the external ac coupling capacitor is required. it?s recommended to be placed near the device transmitter outputs.
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 32 freescale semiconductor enhanced three-speed ethernet (etsec), mii management figure 9. receive input compliance mask figure 10 provides the ac test load for sgmii. figure 10. sgmii ac test/measurement load 8.5 fifo, gmii,mii, tbi, rgmii, rmii, and rtbi ac timing specifications the ac timing specifications for fifo, gmii, mii, tbi, rgmii, rmii, and rtbi are presented in this section. 8.5.1 fifo ac specifications the basis for the ac specifications for the etsec fi fo modes is the double data rate rgmii and rtbi specifications, since they have similar performance a nd are described in a source-synchronous fashion like fifo modes. however, the fifo interface provides de liberate skew between the transmitted data and source clock in gmii fashion. 01 0.275 0.4 0.6 0.725 0 vrx_diffpp_max/2 vrx_diffpp_min/2 ?vrx_diffpp_min/2 ?vrx_diffpp_max/2 time (ui)
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 freescale semiconductor 33 enhanced three-speed ethernet (etsec), mii management when the etsec is configured for fifo modes, all clocks are supplied from external sources to the relevant etsec interface. that is, the transmit clock must be applied to the etsec n tsec n _tx_clk, while the receive clock must be applied to pin tsec n _rx_clk. the etsec internally uses the transmit clock to synchronously generate tr ansmit data and outputs an echoed copy of the transmit clock back out onto the tsec n _gtx_clk pin (while transmit data appears on tsec n _txd[7:0], for example). it is intended that external receivers capture etsec transmit data using the clock on tsec n _gtx_clk as a source-synchronous timing reference. typically, the clock edge that launched the data can be used, since the clock is delayed by the etsec to allow acceptable set-up margin at the receiver. a summary of the fifo ac specifications appears in table 29 and table 30 . table 29. fifo mode transmit ac timing specification at recommended operating conditions with l/tvdd of 3.3 v 5% or 2.5 v 5% parameter/condition symbol min typ max unit notes tx_clk, gtx_clk clock period t fit ?8.0?ns tx_clk, gtx_clk duty cycle t fith 45 50 55 % tx_clk, gtx_clk peak-to-peak jitter t fitj ??250ps rise time tx_clk (20%?80%) t fitr ? ? 0.75 ns fall time tx_clk (80%?20%) t fitf ? ? 0.75 ns gtx_clk to fifo data txd[7:0], tx_er, tx_en hold time t fitdx 0.5 ? 3.0 ns 1 note: 1. data valid t fitdv to gtx_clk min setup time is a function of clock period and max hold time. (min setup = cycle time ? max hold). table 30. fifo mode receive ac timing specification at recommended operating conditions with l/tvdd of 3.3 v 5% or 2.5 v 5% parameter/condition symbol min typ max unit notes rx_clk clock period t fir ?8.0?ns rx_clk duty cycle t firh /t firh 45 50 55 % rx_clk peak-to-peak jitter t firj ??250ps rise time rx_clk (20%?80%) t firr ? ? 0.75 ns fall time rx_clk (80%?20%) t firf ? ? 0.75 ns rxd[7:0], rx_dv, rx_er setup time to rx_clk t firdv 1.5 ? ? ns rx_clk to rxd[7:0], rx_dv, rx_er hold time t firdx 0.5 ? ? ns
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 34 freescale semiconductor enhanced three-speed ethernet (etsec), mii management timing diagrams for fifo appear in figure 11 and figure 12 . . figure 11. fifo transmit ac timing diagram figure 12. fifo receive ac timing diagram 8.5.2 gmii ac timing specifications this section describes the gmii transmit and receive ac timing specifications. 8.5.2.1 gmii transmit ac timing specifications table 31 provides the gmii transmit ac timing specifications. table 31. gmii transmit ac timing specifications at recommended operating conditions with l/tvdd of 3.3 v 5% or 2.5 v 5% parameter/condition symbol 1 min typ max unit notes gtx_clk clock period t gtx ?8.0? ns gtx_clk to gmii data txd[7:0], tx_er, tx_en delay t gtkhdx 0.2 ? 5.0 ns 2 gtx_clk data clock rise time (20%-80%) t gtxr ??1.0ns t fitf txd[7:0] tx_en gtx_clk tx_er t fitdv t fitr t fith t fit t fitdx t firf t firr rx_clk rxd[7:0] rx_dv rx_er valid data t firdx t firdv t firh t fir
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 freescale semiconductor 35 enhanced three-speed ethernet (etsec), mii management figure 13 shows the gmii transmit ac timing diagram. figure 13. gmii transmit ac timing diagram 8.5.2.2 gmii receive ac timing specifications table 32 provides the gmii receive ac timing specifications. gtx_clk data clock fall time (80%-20%) t gtxf ??1.0ns notes: 1. the symbols used for timing specifications follow the pattern t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t gtkhdv symbolizes gmii transmit timing (gt) with respect to the t gtx clock reference (k) going to the high state (h) relative to the time date input signals (d) reaching the valid state (v) to state or setup time. also, t gtkhdx symbolizes gmii transmit timing (gt) with respect to the t gtx clock reference (k) going to the high state (h) relative to the time date input signals (d) going invalid (x) or hold time. note that , in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. for example, the subscript of t gtx represents the gmii(g) transmit (tx) clock. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). 2. data valid t gtkhdv to gtx_clk min setup time is a function of clock period and max hold time (min setup = cycle time ? max delay). table 32. gmii receive ac timing specifications at recommended operating conditions with l/tvdd of 3.3 v 5% or 2.5 v 5% parameter/condition symbol 1 min typ max unit notes rx_clk clock period t grx ?8.0? ns rx_clk duty cycle t grxh /t grx 40 ? 60 % rxd[7:0], rx_dv, rx_er setup time to rx_clk t grdvkh 2.0 ? ? ns rx_clk to rxd[7:0], rx_dv, rx_er hold time t grdxkh 0.5 ? ? ns rx_clk clock rise (20%?80%) t grxr ??1.0ns table 31. gmii transmit ac timing specifications (continued) at recommended operating conditions with l/tvdd of 3.3 v 5% or 2.5 v 5% parameter/condition symbol 1 min typ max unit notes gtx_clk txd[7:0] t gtkhdx t gtx t gtxh t gtxr t gtxf t gtkhdv tx_en tx_er
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 36 freescale semiconductor enhanced three-speed ethernet (etsec), mii management figure 14 provides the ac test load for etsec. figure 14. etsec ac test load figure 15 shows the gmii receive ac timing diagram. figure 15. gmii receive ac timing diagram 8.6 mii ac timing specifications this section describes the mii transmit and receive ac timing specifications. rx_clk clock fall time (80%?20%) t grxf ??1.0ns note: 1. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t grdvkh symbolizes gmii receive timing (gr) with respect to the time data input signals (d) reaching the valid state (v) relative to the t rx clock reference (k) going to the high state (h) or setup time. also, t grdxkl symbolizes gmii receive timing (gr) with respect to the time data input signals (d) went invalid (x) relative to the t grx clock reference (k) going to the low (l) state or hold time. note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. for example, the subscript of t grx represents the gmii (g) receive (rx) clock. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). table 32. gmii receive ac timing specifications (continued) at recommended operating conditions with l/tvdd of 3.3 v 5% or 2.5 v 5% parameter/condition symbol 1 min typ max unit notes output z 0 = 50 lv dd /2 r l = 50 rx_clk rxd[7:0] t grdxkh t grx t grxh t grxr t grxf t grdvkh rx_dv rx_er
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 freescale semiconductor 37 enhanced three-speed ethernet (etsec), mii management 8.6.1 mii transmit ac timing specifications table 33 provides the mii transmit ac timing specifications. figure 16 shows the mii transmit ac timing diagram. figure 16. mii transmit ac timing diagram 8.6.2 mii receive ac timing specifications table 34 provides the mii receive ac timing specifications. table 33. mii transmit ac timing specifications at recommended operating conditions with l/tv dd of 3.3 v 5% or 2.5v 5% parameter/condition symbol 1 min typ max unit notes tx_clk clock period 10 mbps t mtx ?400?ns tx_clk clock period 100 mbps t mtx ?40?ns tx_clk duty cycle t mtxh/ t mtx 35 ? 65 % tx_clk to mii data txd[3:0], tx_er, tx_en delay t mtkhdx 1 5 15 ns tx_clk data clock rise (20%?80%) t mtxr 1.0 ? 4.0 ns tx_clk data clock fall (80%?20%) t mtxf 1.0 ? 4.0 ns note: 1. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t mtkhdx symbolizes mii transmit timing (mt) for the time t mtx clock reference (k) going high (h) until data outputs (d) are invalid (x). note that, in general, the clock reference symbol representation is based on two to three letters representing the clock of a particular functional. for example, the subscript of t mtx represents the mii(m) transmit (tx) clock. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). table 34. mii receive ac timing specifications at recommended operating conditions with l/tvdd of 3.3 v 5%.or 2.5v 5%. parameter/condition symbol 1 min typ max unit notes rx_clk clock period 10 mbps t mrx ?400?ns rx_clk clock period 100 mbps t mrx ?40?ns rx_clk duty cycle t mrxh /t mrx 35 ? 65 % tx_clk txd[3:0] t mtkhdx t mtx t mtxh t mtxr t mtxf tx_en tx_er
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 38 freescale semiconductor enhanced three-speed ethernet (etsec), mii management figure 17 provides the ac test load for etsec. figure 17. etsec ac test load figure 18 shows the mii receive ac timing diagram. figure 18. mii receive ac timing diagram 8.7 tbi ac timing specifications this section describes the tbi trans mit and receive ac timing specifications. rxd[3:0], rx_dv, rx_er setup time to rx_clk t mrdvkh 10.0 ? ? ns rxd[3:0], rx_dv, rx_er hold time to rx_clk t mrdxkh 10.0 ? ? ns rx_clk clock rise (20%?80%) t mrxr 1.0 ? 4.0 ns rx_clk clock fall time (80%?20%) t mrxf 1.0 ? 4.0 ns note: 1. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t mrdvkh symbolizes mii receive timing (mr) with respect to the time data input signals (d) reach the valid state (v) relative to the t mrx clock reference (k) going to the high (h) state or setup time. also, t mrdxkl symbolizes mii receive timing (gr) with respect to the time data input signals (d) went invalid (x) relative to the t mrx clock reference (k) going to the low (l) state or hold time. note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. for example, the subscript of t mrx represents the mii (m) receive (rx) clock. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). table 34. mii receive ac timing specifications (continued) at recommended operating conditions with l/tvdd of 3.3 v 5%.or 2.5v 5%. parameter/condition symbol 1 min typ max unit notes output z 0 = 50 lv dd /2 r l = 50 rx_clk rxd[3:0] t mrdxkl t mrx t mrxh t mrxr t mrxf rx_dv rx_er t mrdvkh valid data
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 freescale semiconductor 39 enhanced three-speed ethernet (etsec), mii management 8.7.1 tbi transmit ac timing specifications table 35 provides the tbi transmit ac timing specifications. figure 19 shows the tbi transmit ac timing diagram. figure 19. tbi transmit ac timing diagram 8.7.2 tbi receive ac timing specifications table 36 provides the tbi receive ac timing specifications. table 35. tbi transmit ac timing specifications at recommended operating conditions with l/tvdd of 3.3 v 5% or 2.5v 5%.. parameter/condition symbol 1 min typ max unit notes gtx_clk clock period t gtx ?8.0?ns gtx_clk to tcg[9:0] delay time t ttkhdx 0.2 ? 5.0 ns 2 gtx_clk rise (20%?80%) t ttxr ??1.0ns gtx_clk fall time (80%?20%) t ttxf ??1.0ns notes: 1. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state )(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t ttkhdv symbolizes the tbi transmit timing (tt) with respect to the time from t ttx (k) going high (h) until the referenced data signals (d) reach the valid state (v) or setup time. also, t ttkhdx symbolizes the tbi transmit timing (tt) with respect to the time from t ttx (k) going high (h) until the referenced data signals (d) reach the invalid state (x) or hold time. note that, in general, the clock refer ence symbol representation is based on three letters representing the clock of a particular functional. for example, the subscript of t ttx represents the tbi (t) transmit (tx) clock. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). 2. data valid t ttkhdv to gtx_clk min setup time is a function of clock period and max hold time (min setup = cycle time ? max delay). table 36. tbi receive ac timing specifications at recommended operating conditions with l/tvdd of 3.3 v 5% or 2.5v 5%. parameter/condition symbol 1 min typ max unit notes pma_rx_clk[0:1] clock period t trx ? 16.0 ? ns pma_rx_clk[0:1] skew t sktrx 7.5 ? 8.5 ns gtx_clk tcg[9:0] t ttx t ttxh t ttxr t ttxf t ttkhdv t ttkhdx
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 40 freescale semiconductor enhanced three-speed ethernet (etsec), mii management figure 20 shows the tbi receive ac timing diagram. figure 20. tbi receive ac timing diagram 8.7.3 tbi single-clock mode ac specifications when the etsec is configured for tbi modes, all cloc ks are supplied from external sources to the relevant etsec interface. in single-clock tbi mode, when tbicon[clksel] = 1a 125-mhz tbi receive clock is supplied on the tsec n _rx_clk pin (no receive clock is used on tsec n _tx_clk in this mode, whereas for the dual-clock mode this is the pma1 receive clock). the 125-mhz transmit clock is applied on the tsec_gtx_clk125 pin in all tbi modes. pma_rx_clk[0:1] duty cycle t trxh /t trx 40 ? 60 % rcg[9:0] setup time to rising pma_rx_clk t trdvkh 2.5 ? ? ns pma_rx_clk to rcg[9:0] hold time t trdxkh 1.5 ? ? ns pma_rx_clk[0:1] clock rise time (20%-80%) t trxr 0.7 ? 2.4 ns pma_rx_clk[0:1] clock fall time (80%-20%) t trxf 0.7 ? 2.4 ns note: 1. the symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t trdvkh symbolizes tbi receive timing (tr) with respect to the time data input signals (d) reach the valid state (v) relative to the t trx clock reference (k) going to the high (h) state or setup time. also, t trdxkh symbolizes tbi receive timing (tr) with respect to the time data input signals (d) went invalid (x) relative to the t trx clock reference (k) going to the high (h) state. note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. for example, the subscript of t trx represents the tbi (t) receive (rx) clock. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). for symbols representing skews, the subscript is skew (sk) followed by the clock that is being skewed (trx). table 36. tbi receive ac timing specifications (continued) at recommended operating conditions with l/tvdd of 3.3 v 5% or 2.5v 5%. parameter/condition symbol 1 min typ max unit notes pma_rx_clk1 rcg[9:0] t trx t trxh t trxr t trxf t trdvkh pma_rx_clk0 t trdxkh t trdvkh t trdxkh t sktrx t trxh valid data valid data
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 freescale semiconductor 41 enhanced three-speed ethernet (etsec), mii management a summary of the single-clock tbi mode ac specifications for receive appears in table 37 . a timing diagram for tbi receive appears in figure 21 . . figure 21. tbi single-clock mode receive ac timing diagram 8.7.4 rgmii and rtbi ac timing specifications table 38 presents the rgmii and rtbi ac timing specifications. table 37. tbi single-clock mode receive ac timing specification parameter/condition symbol min typ max unit notes rx_clk clock period t trr 7.5 8.0 8.5 ns rx_clk duty cycle t trrh 40 50 60 % rx_clk peak-to-peak jitter t trrj ??250ps rise time rx_clk (20%?80%) t trrr ??1.0ns fall time rx_clk (80%?20%) t trrf ??1.0ns rcg[9:0] setup time to rx_clk rising edge t trrdv 2.0??ns rcg[9:0] hold time to rx_clk rising edge t trrdx 1.0??ns table 38. rgmii and rtbi ac timing specifications at recommended operating conditions with l/tv dd of 2.5 v 5%. parameter/condition symbol 1 min typ max unit notes data to clock output skew (at transmitter) t skrgt_tx ?500 0 500 ps 5 data to clock input skew (at receiver) t skrgt_rx 1.0 ? 2.8 ns 2 clock period duration t rgt 7.2 8.0 8.8 ns 3 duty cycle for 10base-t and 100base-tx t rgth /t rgt 40 50 60 % 3, 4 rise time (20%?80%) t rgtr ? ? 0.75 ns rx_clk rcg[9:0] valid data t trrr t trrf t trrdv t trr t trrh t trrdx
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 42 freescale semiconductor enhanced three-speed ethernet (etsec), mii management figure 22 shows the rgmii and rtbi ac timing and multiplexing diagrams. figure 22. rgmii and rtbi ac timing and multiplexing diagrams fall time (20%?80%) t rgtf ? ? 0.75 ns notes: 1. in general, the clock reference symbol representation for this section is based on the symbols rgt to represent rgmii and rtbi timing. for example, the subscript of t rgt represents the tbi (t) receive (rx) clock. note also that the notation for rise (r) and fall (f) times follows the clock symbol that is being represented. for symbols representing skews, the subscript is skew (sk) followed by the clock that is being skewed (rgt). 2. this implies that pc board design will require clocks to be routed such that an additional trace delay of greater than 1.5 ns will be added to the associated clock signal. 3. for 10 and 100 mbps, t rgt scales to 400 ns 40 ns and 40 ns 4 ns, respectively. 4. duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as long as the minimum duty cycle is not violated and stretching occurs for no more than three t rgt of the lowest speed transitioned between. table 38. rgmii and rtbi ac timing specifications (continued) at recommended operating conditions with l/tv dd of 2.5 v 5%. parameter/condition symbol 1 min typ max unit notes gtx_clk t rgt t rgth t skrgt_tx tx_ctl txd[8:5] txd[7:4] txd[9] txerr txd[4] txen txd[3:0] (at transmitter) txd[8:5][3:0] txd[7:4][3:0] tx_clk (at phy) rx_ctl rxd[8:5] rxd[7:4] rxd[9] rxerr rxd[4] rxdv rxd[3:0] rx_clk (at phy) t skrgt_rx t skrgt_rx t skrgt_tx t rgth t rgt gtx_clk (at receiver) rxd[8:5][3:0] rxd[7:4][3:0]
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 freescale semiconductor 43 enhanced three-speed ethernet (etsec), mii management 8.7.5 rmii ac timing specifications this section describes the rmii transmit and receive ac timing specifications. 8.7.5.1 rmii transmit ac timing specifications the rmii transmit ac timing specifications are in table 39 . figure 23 shows the rmii transmit ac timing diagram. figure 23. rmii transmit ac timing diagram 8.7.5.2 rmii receive ac timing specifications table 39. rmii transmit ac timing specifications at recommended operating conditions with l/tv dd of 3.3 v 5% or 2.5v 5%. parameter/condition symbol 1 min typ max unit notes ref_clk clock period t rmt 15.0 20.0 25.0 ns ref_clk duty cycle t rmth 35 50 65 % ref_clk peak-to-peak jitter t rmtj ? ? 250 ps rise time ref_clk (20%?80%) t rmtr 1.0 ? 2.0 ns fall time ref_clk (80%?20%) t rmtf 1.0 ? 2.0 ns ref_clk to rmii data txd[1:0], tx_en delay t rmtdx 1.0 ? 10.0 ns note: 1. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t mtkhdx symbolizes mii transmit timing (mt) for the time t mtx clock reference (k) going high (h) until data outputs (d) are invalid (x). note that, in general, the clock reference symbol representation is based on two to three letters representing the clock of a particular functional. for example, the subscript of t mtx represents the mii(m) transmit (tx) clock. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). table 40. rmii receive ac timing specifications at recommended operating conditions with l/tv dd of 3.3 v 5%.or 2.5v 5%. parameter/condition symbol 1 min typ max unit notes ref_clk clock period t rmr 15.0 20.0 25.0 ns ref_clk duty cycle t rmrh 35 50 65 % ref_clk txd[1:0] t rmtdx t rmt t rmth t rmtr t rmtf tx_en tx_er
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 44 freescale semiconductor enhanced three-speed ethernet (etsec), mii management figure 24 provides the ac test load for etsec. figure 24. etsec ac test load figure 25 shows the rmii receive ac timing diagram. figure 25. rmii receive ac timing diagram ref_clk peak-to-peak jitter t rmrj ??250ps rise time ref_clk (20%?80%) t rmrr 1.0 ? 2.0 ns fall time ref_clk (80%?20%) t rmrf 1.0 ? 2.0 ns rxd[1:0], crs_dv, rx_er setup time to ref_clk rising edge t rmrdv 4.0 ? ? ns rxd[1:0], crs_dv, rx_er hold time to ref_clk rising edge t rmrdx 2.0 ? ? ns note: 1. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t mrdvkh symbolizes mii receive timing (mr) with respect to the time data input signals (d) reach the valid state (v) relative to the t mrx clock reference (k) going to the high (h) state or setup time. also, t mrdxkl symbolizes mii receive timing (gr) with respect to the time data input signals (d) went invalid (x) relative to the t mrx clock reference (k) going to the low (l) state or hold time. note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. for example, the subscript of t mrx represents the mii (m) receive (rx) clock. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). table 40. rmii receive ac timing specifications (continued) at recommended operating conditions with l/tv dd of 3.3 v 5%.or 2.5v 5%. parameter/condition symbol 1 min typ max unit notes output z 0 = 50 lv dd /2 r l = 50 ref_clk rxd[1:0] t rmrdx t rmr t rmrh t rmrr t rmrf crs_dv rx_er t rmrdv valid data
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 freescale semiconductor 45 ethernet management interface electrical characteristics 9 ethernet management interface electrical characteristics the electrical characteristics specified here apply to mii management interface signals mdio (management data input/output) and mdc (management data clock). the electrical characteristics for gmii, rgmii, rmii, tbi, and rtbi are specified in ? section 8, ?enhanced three-speed ethernet (etsec), mii management.? 9.1 mii management dc electrical characteristics the mdc and mdio are defined to operate at a supply vo ltage of 3.3 v. the dc electrical characteristics for mdio and mdc are provided in table 41 . 9.2 mii management ac electrical specifications table 42 provides the mii management ac timing specifications. table 41. mii management dc electrical characteristics parameter symbol min max unit notes supply voltage (3.3 v) ov dd 3.135 3.465 v output high voltage (ov dd = min, i oh = ?1.0 ma) v oh 2.10 3.60 v output low voltage (ov dd = min, i ol = 1.0 ma) v ol gnd 0.50 v input high voltage v ih 1.95 ? v input low voltage v il ?0.90v input high current (ov dd = max, v in = 2.1 v) i ih ?40 a1 input low current (ov dd = max, v in = 0.5 v) i il ?600 ? a note: 1. the symbol v in , in this case, represents the ov in symbol referenced in ta b l e 1 and ta b l e 2 . table 42. mii management ac timing specifications at recommended operating conditions with ov dd is 3.3 v 5%. parameter/condition symbol 1 min typ max unit notes mdc frequency f mdc ?2.5?mhz2 mdc period t mdc ?400?ns mdc clock pulse width high t mdch 32 ? ? ns mdc to mdio delay t mdkhdx (16 * t plb_clk ) ? 3 ? (16 * t plb_clk ) + 3 ns 3, 4 mdio to mdc setup time t mddvkh 5??ns mdio to mdc hold time t mddxkh 0??ns mdc rise time t mdcr ? ? 10 ns
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 46 freescale semiconductor ethernet management interface electrical characteristics figure 26 shows the mii management ac timing diagram. figure 26. mii management interface timing diagram mdc fall time t mdhf ? ? 10 ns notes: 1. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t mdkhdx symbolizes management data timing (md) for the time t mdc from clock reference (k) high (h) until data outputs (d) are invalid (x) or data hold time. also, t mddvkh symbolizes management data timing (md) with respect to the time data input signals (d) reach the valid state (v) relative to the t mdc clock reference (k) going to the high (h) state or setup time. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). 2. this parameter is dependent on the platform clock frequency (miimcfg [mgmtclk] field determines the clock frequency of the mgmtclk clock ec_mdc). 3. this parameter is dependent on the platform clock frequency. the delay is equal to 16 platform clock periods 3 ns. for example, with a platform clock of 333 mhz, the min/max delay is 48 ns 3 ns. similarly, if the platform clock is 400 mhz, the min/max delay is 40 ns 3 ns). 4. t plb_clk is the platform (ccb) clock. table 42. mii management ac timing specifications (continued) at recommended operating conditions with ov dd is 3.3 v 5%. parameter/condition symbol 1 min typ max unit notes mdc t mddxkh t mdc t mdch t mdcr t mdcf t mddvkh t mdkhdx mdio mdio (input) (output)
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 freescale semiconductor 47 local bus 10 local bus this section describes the dc and ac electrical specifications for the local bus interface of the mpc8544e. 10.1 local bus dc electrical characteristics table 43 provides the dc electrical characteristics for the local bus interface operating at bv dd =3.3vdc. table 44 provides the dc electrical characteristics for the local bus interface operating at bv dd =2.5vdc. table 45 provides the dc electrical characteristics for the local bus interface operating at bv dd =1.8vdc. table 43. local bus dc electrical characteristics (3.3 v dc) parameter symbol min max unit notes high-level input voltage v ih 2bv dd + 0.3 v low-level input voltage v il ?0.3 0.8 v input current (bv in = 0 v or bv in = bov dd )i in ?5 a1 high-level output voltage (bv dd = min, i oh = ?2 ma) v oh 2.4 ? v low-level output voltage (bv dd = min, i ol = 2 ma) v ol ?0.4v note: 1. the symbol bv in , in this case, represents the bv in symbol referenced in ta ble 1 and ta ble 2 . table 44. local bus dc electrical characteristics (2.5 v dc) parameter symbol min max unit notes high-level input voltage v ih 1.70 bv dd + 0.3 v low-level input voltage v il ?0.3 0.7 v input current (bv in = 0 v or bv in = bv dd )i in ? 15 a1 high-level output voltage (bv dd = min, i oh = ?1 ma) v oh 2.0 ? v low-level output voltage (bv dd = min, i ol = 1 ma) v ol ?0.4v note: 1. the symbol bv in , in this case, represents the bv in symbol referenced in ta ble 1 and ta ble 2 . table 45. local bus dc electrical characteristics (1.8 v dc) parameter symbol min max unit notes high-level input voltage v ih 1.3 bv dd + 0.3 v low-level input voltage v il ?0.3 0.6 v input current (bv in = 0 v or bv in = bv dd )i in ?15 a1
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 48 freescale semiconductor local bus 10.2 local bus ac electrical specifications table 46 describes the general timing parameters of the local bus interface at bv dd = 3.3 v. for information about the frequency range of local bus see section 19.1, ?clock ranges .? high-level output voltage (bv dd = min, i oh = ?2 ma) v oh 1.35 ? v low-level output voltage (bv dd = min, i ol = 2 ma) v ol ?0.45v table 46. local bus general timing parameters (bv dd =3.3 v) ?pll enabled parameter symbol 1 min max unit notes local bus cycle time t lbk 7.5 12 ns 2 local bus duty cycle t lbkh/ t lbk 43 57 % lclk[n] skew to lclk[m] or lsync_out t lbkskew ? 150 ps 7, 8 input setup to local bus clock (except lupwait) t lbivkh1 2.5 ? ns 3, 4 lupwait input setup to local bus clock t lbivkh2 1.85 ? ns 3, 4 input hold from local bus clock (except lupwait) t lbixkh1 1.0 ? ns 3, 4 lupwait input hold from local bus clock t lbixkh2 1.0 ? ns 3, 4 lale output transition to lad/ldp output transition (latch setup and hold time) t lbotot 1.5 ? ns 6 local bus clock to output valid (except lad/ldp and lale) t lbkhov1 ?2.9ns local bus clock to data valid for lad/ldp t lbkhov2 ?2.8ns3 local bus clock to address valid for lad t lbkhov3 ?2.7ns3 local bus clock to lale assertion t lbkhov4 ?2.7ns3 output hold from local bus clock (except lad/ldp and lale) t lbkhox1 0.7 ? ns 3 output hold from local bus clock for lad/ldp t lbkhox2 0.7 ? ns 3 local bus clock to output high impedance (except lad/ldp and lale) t lbkhoz1 ?2.5ns5 table 45. local bus dc electrical characteristics (1.8 v dc) (continued) parameter symbol min max unit notes
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 freescale semiconductor 49 local bus table 47 describes the general timing parameters of the local bus interface at bv dd = 2.5 v. local bus clock to output high impedance for lad/ldp t lbkhoz2 ?2.5ns5 notes: 1. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t lbixkh1 symbolizes local bus timing (lb) for the input (i) to go invalid (x) with respect to the time the t lbk clock reference (k) goes high (h), in this case for clock one (1). also, t lbkhox symbolizes local bus timing (lb) for the t lbk clock reference (k) to go high (h), with respect to the output (o) going invalid (x) or output hold time. 2. all timings are in reference to lsync_in for pll enabled and internal local bus clock for pll bypass mode. 3. all signals are measured from bv dd /2 of the rising edge of lsync_in for pll enabled or internal local bus clock for pll bypass mode to 0.4 bv dd of the signal in question for 3.3-v signaling levels. 4. input timings are measured at the pin. 5. for purposes of active/float timing measurements, the hi-z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 6. t lbotot is a measurement of the minimum time between the negation of lale and any change in lad. t lbotot is programmed with the lbcr[ahd] parameter. 7. maximum possible clock skew between a clock lclk[m] and a relative clock lclk[n]. skew measured between complementary signals at bv dd /2. table 47. local bus general timing parameters (bv dd =2.5v) ?pll enabled parameter symbol 1 min max unit notes local bus cycle time t lbk 7.5 12 ns 2 local bus duty cycle t lbkh/ t lbk 43 57 % lclk[n] skew to lclk[m] or lsync_out t lbkskew ? 150 ps 7 input setup to local bus clock (except lupwait) t lbivkh1 2.4 ? ns 3, 4 lupwait input setup to local bus clock t lbivkh2 1.8 ? ns 3, 4 input hold from local bus clock (except lupwait) t lbixkh1 1.1 ? ns 3, 4 lupwait input hold from local bus clock t lbixkh2 1.1 ? ns 3, 4 lale output transition to lad/ldp output transition (latch setup and hold time) t lbotot 1.5 ? ns 6 local bus clock to output valid (except lad/ldp and lale) t lbkhov1 ?2.8ns local bus clock to data valid for lad/ldp t lbkhov2 ?2.8ns3 local bus clock to address valid for lad t lbkhov3 ?2.8ns3 local bus clock to lale assertion t lbkhov4 ?2.8ns3 output hold from local bus clock (except lad/ldp and lale) t lbkhox1 0.8 ? ns 3 output hold from local bus clock for lad/ldp t lbkhox2 0.8 ? ns 3 local bus clock to output high impedance (except lad/ldp and lale) t lbkhoz1 ?2.6ns5 table 46. local bus general timing parameters (bv dd =3.3 v) ?pll enabled (continued) parameter symbol 1 min max unit notes
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 50 freescale semiconductor local bus table 48 describes the general timing parameters of the local bus interface at bv dd = 1.8 v dc. local bus clock to output high impedance for lad/ldp t lbkhoz2 ?2.6ns5 notes: 1. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t lbixkh1 symbolizes local bus timing (lb) for the input (i) to go invalid (x) with respect to the time the t lbk clock reference (k) goes high (h), in this case for clock one (1). also, t lbkhox symbolizes local bus timing (lb) for the t lbk clock reference (k) to go high (h), with respect to the output (o) going invalid (x) or output hold time. 2. all timings are in reference to lsync_in for pll enabled and internal local bus clock for pll bypass mode. 3. all signals are measured from bv dd /2 of the rising edge of lsync_in for pll enabled or internal local bus clock for pll bypass mode to 0.4 bv dd of the signal in question for 2.5-v signaling levels. 4. input timings are measured at the pin. 5. for purposes of active/float timing measurements, the hi-z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 6. t lbotot is a measurement of the minimum time between the negation of lale and any change in lad. t lbotot is programmed with the lbcr[ahd] parameter. 7. maximum possible clock skew between a clock lclk[m] and a relative clock lclk[n]. skew measured between complementary signals at bv dd /2. table 48. local bus general timing parameters (bv dd = 1.8 v dc) parameter symbol 1 min max unit notes local bus cycle time t lbk 7.5 12 ns 2 local bus duty cycle t lbkh/ t lbk 43 57 % lclk[n] skew to lclk[m] or lsync_out t lbkskew ? 150 ps 7 input setup to local bus clock (except lupwait) t lbivkh1 2.6 ? ns 3, 4 lupwait input setup to local bus clock t lbivkh2 1.9 ? ns 3, 4 input hold from local bus clock (except lupwait) t lbixkh1 1.1 ? ns 3, 4 lupwait input hold from local bus clock t lbixkh2 1.1 ? ns 3, 4 lale output transition to lad/ldp output transition (latch setup and hold time) t lbotot 1.2 ? ns 6 local bus clock to output valid (except lad/ldp and lale) t lbkhov1 ?3.2ns local bus clock to data valid for lad/ldp t lbkhov2 ?3.2ns3 local bus clock to address valid for lad t lbkhov3 ?3.2ns3 local bus clock to lale assertion t lbkhov4 3.2 ns 3 output hold from local bus clock (except lad/ldp and lale) t lbkhox1 0.9 ? ns 3 output hold from local bus clock for lad/ldp t lbkhox2 0.9 ? ns 3 local bus clock to output high impedance (except lad/ldp and lale) t lbkhoz1 ?2.6ns5 table 47. local bus general timing parameters (bv dd =2.5v) ?pll enabled (continued) parameter symbol 1 min max unit notes
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 freescale semiconductor 51 local bus figure 27 provides the ac test load for the local bus. figure 27. local bus ac test load local bus clock to output high impedance for lad/ldp t lbkhoz2 ?2.6ns5 notes: 1. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t lbixkh1 symbolizes local bus timing (lb) for the input (i) to go invalid (x) with respect to the time the t lbk clock reference (k) goes high (h), in this case for clock one (1). also, t lbkhox symbolizes local bus timing (lb) for the t lbk clock reference (k) to go high (h), with respect to the output (o) going invalid (x) or output hold time. 2. all timings are in reference to lsync_in for pll enabled and internal local bus clock for pll bypass mode. 3. all signals are measured from bv dd /2 of the rising edge of lsync_in for pll enabled or internal local bus clock for pll bypass mode to 0.4 bv dd of the signal in question for 1.8-v signaling levels. 4. input timings are measured at the pin. 5. for purposes of active/float timing measurements, the hi-z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 6. t lbotot is a measurement of the minimum time between the negation of lale and any change in lad. t lbotot is programmed with the lbcr[ahd] parameter. 7. maximum possible clock skew between a clock lclk[m] and a relative clock lclk[n]. skew measured between complementary signals at bv dd /2. table 48. local bus general timing parameters (bv dd = 1.8 v dc) (continued) parameter symbol 1 min max unit notes output z 0 = 50 bv dd /2 r l = 50
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 52 freescale semiconductor local bus figure 28 to figure 33 show the local bus signals. figure 28. local bus signals (pll enabled) table 49 describes the general timing parameters of the local bus interface at v dd = 3.3 v dc with pll disabled. table 49. local bus general timing parameters?pll bypassed parameter symbol 1 min max unit notes local bus cycle time t lbk 12 ? ns 2 local bus duty cycle t lbkh/ t lbk 43 57 % internal launch/capture clock to lclk delay t lbkhkt 1.2 4.9 ns input setup to local bus clock (except lupwait) t lbivkh1 7.4 ? ns 4, 5 lupwait input setup to local bus clock t lbivkl2 6.75 ? ns 4, 5 input hold from local bus clock (except lupwait) t lbixkh1 ?0.2 ? ns 4, 5 lupwait input hold from local bus clock t lbixkl2 ?0.2 ? ns 4, 5 lale output transition to lad/ldp output transition (latch hold time) t lbotot 1.5 ? ns 6 local bus clock to output valid (except lad/ldp and lale) t lbklov1 ? 1.6ns output signals: la[27:31]/lbctl/lbcke/loe / lsda10/lsdwe/lsdras / lsdcas /lsddqm[0:3] t lbkhov1 t lbkhov2 t lbkhov3 lsync_in input signals: lad[0:31]/ldp[0:3] output (data) signals: lad[0:31]/ldp[0:3] output (address) signal: lad[0:31] lale t lbixkh1 t lbivkh1 t lbivkh2 t lbixkh2 t lbkhox1 t lbkhoz1 t lbkhox2 t lbkhoz2 input signal: lgta t lbotot t lbkhoz2 t lbkhox2 t lbkhov4 lupwait
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 freescale semiconductor 53 local bus local bus clock to data valid for lad/ldp t lbklov2 ? 1.6ns4 local bus clock to address valid for lad, and lale t lbklov3 ? 1.6ns4 output hold from local bus clock (except lad/ldp and lale) t lbklox1 ?4.1 ? ns 4 output hold from local bus clock for lad/ldp t lbklox2 ?4.1 ? ns 4 local bus clock to output high impedance (except lad/ldp and lale) t lbkloz1 ? 1.4ns7 local bus clock to output high impedance for lad/ldp t lbkloz2 ? 1.4ns7 notes: 1. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t lbixkh1 symbolizes local bus timing (lb) for the input (i) to go invalid (x) with respect to the time the t lbk clock reference (k) goes high (h), in this case for clock one (1). also, t lbkhox symbolizes local bus timing (lb) for the t lbk clock reference (k) to go high (h), with respect to the output (o) going invalid (x) or output hold time. 2. all timings are in reference to local bus clock for pll bypass mode. timings may be negative with respect to the local bus clock because the actual launch and capture of signals is done with the internal launch/capture clock, which proceeds lclk by t lbkhkt . 3. maximum possible clock skew between a clock lclk[m] and a relative clock lclk[n]. skew measured between complementary signals at bv dd /2. 4. all signals are measured from bv dd /2 of the rising edge of local bus clock for pll bypass mode to 0.4 x bv dd of the signal in question for 3.3-v signaling levels. 5. input timings are measured at the pin. 6. the value of t lbotot is the measurement of the minimum time between the negation of lale and any change in lad. 7. for purposes of active/float timing measurements, the hi-z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. table 49. local bus general timing parameters?pll bypassed (continued) parameter symbol 1 min max unit notes
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 54 freescale semiconductor local bus figure 29. local bus signals (pll bypass mode) note in pll bypass mode, lclk[n] is the inverted version of the internal clock with the delay of t lbkhkt . in this mode, signals are launched at the rising edge of the internal clock and are capt ured at falling edge of the internal clock withe the exception of lgta /lupwait (which is captured on the rising edge of the internal clock). output signals: la[27:31]/lbctl/lbcke/loe / lsda10/lsdwe/lsdras / lsdcas /lsddqm[0:3] t lbklov2 lclk[n] input signals: lad[0:31]/ldp[0:3] output (data) signals: lad[0:31]/ldp[0:3] lale t lbixkh1 input signal: lgta output (address) signal: lad[0:31] t lbivkh1 t lbixkl2 t lbivkl2 t lbklox1 t lbkloz2 t lbotot internal launch/capture clock t lbklox2 t lbklov1 t lbklov3 t lbkloz1 t lbkhkt lupwait
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 freescale semiconductor 55 local bus figure 30. local bus signals, gpcm/upm signals for lccr[clkdiv] = 4 (pll enabled) lsync_in upm mode input signal: lupwait t lbixkh2 t lbivkh2 t lbivkh1 t lbixkh1 t lbkhoz1 t1 t3 input signals: lad[0:31]/ldp[0:3] upm mode output signals: lcs [0:7]/lbs [0:3]/lgpl[0:5] gpcm mode output signals: lcs [0:7]/lwe t lbkhov1 t lbkhov1 t lbkhoz1 gpcm mode input signal: lgta
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 56 freescale semiconductor local bus figure 31. local bus si gnals, gpcm/upm signals for lccr[clkdiv] = 4 (pll bypass mode) t lbivkh1 t lbixkl2 internal launch/capture clock upm mode input signal: lupwait t1 t3 input signals: lad[0:31]/ldp[0:3] upm mode output signals: lcs [0:7]/lbs [0:3]/lgpl[0:5] gpcm mode output signals: lcs [0:7]/lwe t lbklov1 t lbkloz1 lclk t lbklox1 t lbixkh1 gpcm mode input signal: lgta t lbivkl2
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 freescale semiconductor 57 local bus figure 32. local bus signals, gpcm/upm signal s for lccr[clkdiv] = 8 or 16 (pll enabled) lsync_in upm mode input signal: lupwait t lbixkh2 t lbivkh2 t lbivkh1 t lbixkh1 t lbkhoz1 t1 t3 upm mode output signals: lcs [0:7]/lbs [0:3]/lgpl[0:5] gpcm mode output signals: lcs [0:7]/lwe t lbkhov1 t lbkhov1 t lbkhoz1 t2 t4 input signals: lad[0:31]/ldp[0:3] gpcm mode input signal: lgta
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 58 freescale semiconductor programmable interrupt controller figure 33. local bus signals, gpcm/upm signals for lccr[clkdiv] = 8 or 16 (pll bypass mode) 11 programmable interrupt controller in irq edge trigger mode, when an external interr upt signal is asserted (according to the programmed polarity), it must remain the assertion for at least 3 system clocks (sysclk periods). t lbixkl2 t lbivkh1 internal launch/capture clock upm mode input signal: lupwait t1 t3 upm mode output signals: lcs [0:7]/lbs [0:3]/lgpl[0:5] gpcm mode output signals: lcs [0:7]/lwe t2 t4 input signals: lad[0:31]/ldp[0:3] lclk t lbklov1 t lbkloz1 t lbklox1 t lbixkh1 gpcm mode input signal: lgta t lbivkl2
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 freescale semiconductor 59 jtag 12 jtag this section describes the ac electrical specifica tions for the ieee 1149.1 (jtag) interface of the mpc8544e. 12.1 jtag dc electrical characteristics table 43 provides the dc electrical characteristics for the jtag interface. 12.2 jtag ac electrical specifications table 51 provides the jtag ac timing specifications as defined in figure 34 through figure 37 . table 50. jtag dc electrical characteristics parameter symbol min max unit notes high-level input voltage v ih 2bv dd + 0.3 v low-level input voltage v il ?0.3 0.8 v input current (bv in = 0 v or bv in = bov dd )i in ?5 a1 high-level output voltage (bv dd = min, i oh = ?2 ma) v oh 2.4 ? v low-level output voltage (bv dd = min, i ol = 2 ma) v ol ?0.4v note: 1. note that the symbol v in , in this case, represents the ov in . table 51. jtag ac timing specifications (independent of sysclk) 1 at recommended operating conditions (see ta b l e 3 ). parameter symbol 2 min max unit notes jtag external clock frequency of operation f jtg 0 33.3 mhz jtag external clock cycle time t jtg 30 ? ns jtag external clock pulse width measured at 1.4 v t jtkhkl 15 ? ns jtag external clock rise and fall times t jtgr & t jtgf 02ns trst assert time t trst 25 ? ns 3 input setup times: boundary-scan data tms, tdi t jtdvkh t jtivkh 4 0 ? ? ns 4 input hold times: boundary-scan data tms, tdi t jtdxkh t jtixkh 20 25 ? ? ns 4 valid times: boundary-scan data tdo t jtkldv t jtklov 4 4 20 25 ns 5
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 60 freescale semiconductor jtag figure 34 provides the ac test load for tdo and the boundary-scan outputs. figure 34. ac test load for the jtag interface figure 35 provides the jtag clock input timing diagram. figure 35. jtag clock input timing diagram output hold times: boundary-scan data tdo t jtkldx t jtklox 4 4 ? ? ns 5 jtag external clock to output high impedance: boundary-scan data tdo t jtkldz t jtkloz 3 3 19 9 ns 5 notes: 1. all outputs are measured from the midpoint voltage of the falling/rising edge of t tclk to the midpoint of the signal in question. the output timings are measured at the pins. all output timings assume a purely resistive 50- load (see figure 34 ). time-of-flight delays must be added for trace lengths, vias, and connectors in the system. 2. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t jtdvkh symbolizes jtag device timing (jt) with respect to the time data input signals (d) reaching the valid state (v) relative to the t jtg clock reference (k) going to the high (h) state or setup time. also, t jtdxkh symbolizes jtag timing (jt) with respect to the time data input signals (d) went invalid (x) relative to the t jtg clock reference (k) going to the high (h) state. note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). 3. trst is an asynchronous level sensitive signal. the setup time is for test purposes only. 4. non-jtag signal input timing with respect to t tclk . 5. non-jtag signal output timing with respect to t tclk . table 51. jtag ac timing specifications (independent of sysclk) 1 (continued) at recommended operating conditions (see ta b l e 3 ). parameter symbol 2 min max unit notes output z 0 = 50 ov dd /2 r l = 50 jtag t jtkhkl t jtgr external clock vm vm vm t jtg t jtgf vm = midpoint voltage (ov dd /2)
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 freescale semiconductor 61 i 2 c figure 36 provides the trst timing diagram. figure 36. trst timing diagram figure 37 provides the boundary-scan timing diagram. figure 37. boundary-scan timing diagram 13 i 2 c this section describes the dc and ac electrical characteristics for the i 2 c interfaces of the mpc8544e. 13.1 i 2 c dc electrical characteristics table 52 provides the dc electrical characteristics for the i 2 c interfaces. table 52. i 2 c dc electrical characteristics at recommended operating conditions with ov dd of 3.3 v 5%. parameter symbol min max unit notes input high voltage level v ih 0.7 ov dd ov dd +0.3 v input low voltage level v il ?0.3 0.3 ov dd v low level output voltage v ol 00.2 ov dd v1 pulse width of spikes which must be suppressed by the input filter t i2khkl 050ns2 trst vm = midpoint voltage (ov dd /2) vm vm t trst vm = midpoint voltage (ov dd /2) vm vm t jtdvkh t jtdxkh boundary data outputs boundary data outputs jtag external clock boundary data inputs output data valid t jtkldx t jtkldz t jtkldv input data valid output data valid
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 62 freescale semiconductor i 2 c 13.2 i 2 c ac electrical specifications table 53 provides the ac timing parameters for the i 2 c interfaces. input current each i/o pin (input voltage is between 0.1 ov dd and 0.9 ov dd (max) i i ?10 10 a3 capacitance for each i/o pin c i ?10pf notes: 1. output voltage (open drain or open collector) condition = 3 ma sink current. 2. refer to the mpc8544e powerquicc iii integrated communications host processor reference manual for information on the digital filter used. 3. i/o pins will obstruct the sda and scl lines if ov dd is switched off. table 53. i 2 c ac electrical specifications all values refer to v ih (min) and v il (max) levels (see ta b l e 5 2 ). parameter symbol 1 min max unit notes scl clock frequency f i2c 0400khz low period of the scl clock t i2cl 1.3 ? s high period of the scl clock t i2ch 0.6 ? s setup time for a repeated start condition t i2svkh 0.6 ? s hold time (repeated) start condition (after this period, the first clock pulse is generated) t i2sxkl 0.6 ? s data setup time t i2dvkh 100 ? ns data hold time: cbus compatible masters i 2 c bus devices t i2dxkl ? 0 ? ? s2 data output delay time t i2ovkl ?0.9 3 set-up time for stop condition t i2pvkh 0.6 ? s rise time of both sda and scl signals t i2cr 20 + 0.1 c b 300 ns 4 fall time of both sda and scl signals t i2cf 20 + 0.1 c b 300 ns 4 bus free time between a stop and start condition t i2khdx 1.3 ? s noise margin at the low level for each connected device (including hysteresis) v nl 0.1 ov dd ?v table 52. i 2 c dc electrical characteristics (continued) at recommended operating conditions with ov dd of 3.3 v 5%. parameter symbol min max unit notes
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 freescale semiconductor 63 i 2 c figure 38 provides the ac test load for the i 2 c. figure 38. i 2 c ac test load figure 39 shows the ac timing diagram for the i 2 c bus. figure 39. i 2 c bus ac timing diagram noise margin at the high level for each connected device (including hysteresis) v nh 0.2 ov dd ?v notes: 1. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t i2dvkh symbolizes i 2 c timing (i2) with respect to the time data input signals (d) reach the valid state (v) relative to the t i2c clock reference (k) going to the high (h) state or setup time. also, t i2sxkl symbolizes i 2 c timing (i2) for the time that the data with respect to the start condition (s) went invalid (x) relative to the t i2c clock reference (k) going to the low (l) state or hold time. also, t i2pvkh symbolizes i 2 c timing (i2) for the time that the data with respect to the stop condition (p) reaching the valid state (v) relative to the t i2c clock reference (k) going to the high (h) state or setup time. for rise and fall times, the latter convention is used with the approp riate letter: r (rise) or f (fall). 2. the mpc8544e provides a hold time of at least 300 ns for the sda signal (referred to the v ih min of the scl signal) to bridge the undefined region of the falling edge of scl. 3. the maximum t i2dxkl has only to be met if the device does not stretch the low period (t i2cl ) of the scl signal. 4. c b = capacitance of one bus line in pf. table 53. i 2 c ac electrical specifications (continued) all values refer to v ih (min) and v il (max) levels (see ta b l e 5 2 ). parameter symbol 1 min max unit notes output z 0 = 50 ov dd /2 r l = 50 sr s sda scl t i2cf t i2sxkl t i2cl t i2ch t i2dxkl, t i2oxkl t i2dvkh t i2sxkl t i2svkh t i2khkl t i2pvkh t i2cr t i2cf ps
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 64 freescale semiconductor gpio 14 gpio this section describes the dc and ac electrical sp ecifications for the gpio interface of the mpc8544e. 14.1 gpio dc electrical characteristics table 54 provides the dc electrical characteristics for the gpio interface. 14.2 gpio ac electrical specifications table 55 provides the gpio input and output ac timing specifications. figure 40 provides the ac test load for the gpio. figure 40. gpio ac test load table 54. gpio dc electrical characteristics parameter symbol min max unit notes high-level input voltage v ih 2ov dd + 0.3 v low-level input voltage v il ? 0.3 0.8 v input current (v in = 0 v or v in = v dd) i in ?5 a1 high-level output voltage (ov dd = mn, i oh = ?2 ma) v oh 2.4 ? v low-level output voltage (ov dd = min, i ol = 2 ma) v ol ?0.4v note: 1. note that the symbol v in , in this case, represents the ov in symbol referenced in ta b l e 1 and ta b l e 2 . table 55. gpio input ac timing specifications 1 parameter symbol typ unit notes gpio inputs?minimum pulse width t piwid 20 ns 2 notes: 1. input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of sysclk. timings are measured at the pin. 2. gpio inputs and outputs are asynchronous to any visible clock. gpio outputs should be synchronized before use by any external synchronous logic. gpio inputs are required to be valid for at least t piwid ns to ensure proper operation. output z 0 = 50 ov dd /2 r l = 50
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 freescale semiconductor 65 pci 15 pci this section describes the dc and ac electrical specifications for the pci bus of the mpc8544e. 15.1 pci dc electrical characteristics table 56 provides the dc electrical characteristics for the pci interface. 15.2 pci ac electrical specifications this section describes the general ac timing parameters of the pci bus. note that the sysclk signal is used as the pci input clock. table 57 provides the pci ac timing specifications at 66 mhz. table 56. pci dc electrical characteristics 1 parameter symbol min max unit notes high-level input voltage v ih 2ov dd + 0.3 v low-level input voltage v il ?0.3 0.8 v input current (v in = 0 v or v in = v dd )i in ?5 a2 high-level output voltage (ov dd = min, i oh = ?2ma) v oh 2.4 ? v low-level output voltage (ov dd = min, i ol = 2 ma) v ol ?0.4v notes: 1. ranges listed do not meet the full range of the dc specifications of the pci 2.2 local bus specifications . 2. note that the symbol v in , in this case, represents the ov in symbol referenced in ta b l e 1 and ta b l e 2 . table 57. pci ac timing specifications at 66 mhz parameter symbol 1 min max unit notes sysclk to output valid t pckhov ? 7.4 ns 2, 3 output hold from sysclk t pckhox 2.0 ? ns 2 sysclk to output high impedance t pckhoz ?14ns2, 4 input setup to sysclk t pcivkh 3.7 ? ns 2, 5 input hold from sysclk t pcixkh 0.5 ? ns 2, 5 req64 to hreset 9 setup time t pcrvrh 10 t sys ?clocks6, 7 hreset to req64 hold time t pcrhrx 050ns7 hreset high to first frame assertion t pcrhfv 10 ? clocks 8 rise time (20%?80%) t pciclk 0.6 2.1 ns
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 66 freescale semiconductor pci figure 41 provides the ac test load for pci. figure 41. pci ac test load figure 42 shows the pci input ac timing conditions. figure 42. pci input ac timing measurement conditions fall time (20%?80%) t pciclk 0.6 2.1 ns notes: 1. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t pcivkh symbolizes pci timing (pc) with respect to the time the input signals (i) reach the valid state (v) relative to the sysclk clock, t sys , reference (k) going to the high (h) state or setup time. also, t pcrhfv symbolizes pci timing (pc) with respect to the time hard reset (r) went high (h) relative to the frame signal (f) going to the valid (v) state. 2. see the timing measurement conditions in the pci 2.2 local bus specifications . 3. all pci signals are measured from ov dd /2 of the rising edge of pci_sync_in to 0.4 ov dd of the signal in question for 3.3-v pci signaling levels. 4. for purposes of active/float timing measurements, the hi-z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 5. input timings are measured at the pin. 6. the timing parameter t sys indicates the minimum and maximum clk cycle times for the various specified frequencies. the system clock period must be kept within the minimum and maximum defined ranges. for values see section 19, ?clocking.? 7. the setup and hold time is with respect to the rising edge of hreset . 8. the timing parameter t pcrhfv is a minimum of 10 clocks rather than the minimum of 5 clocks in the pci 2.2 local bus specifications . 9. the reset assertion timing requirement for hreset is 100 s. table 57. pci ac timing specifications at 66 mhz (continued) parameter symbol 1 min max unit notes output z 0 = 1 k ov dd /2 r l = 50 t pcivkh clk input t pcixkh
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 freescale semiconductor 67 high-speed serial interfaces (hssi) figure 43 shows the pci output ac timing conditions. figure 43. pci output ac timing measurement condition 16 high-speed serial interfaces (hssi) the mpc8544e features two serializer/deserializer (serdes) interfaces to be used for high-speed serial interconnect applications.the serdes1 dedicated for pci express data transfers. the serdes2 can be used for pci express and/or sgmii application. th is section describes the common portion of serdes dc electrical specifications, which is the dc requireme nt for serdes reference clocks. the serdes data lane?s transmitter and receiver reference circuits are also shown. 16.1 signal terms definition the serdes utilizes differential signaling to transfer data across the serial link. this section defines terms used in the description and specification of differential signals. figure 44 shows how the signals are defined. for illustration purpose, only one serdes lane is used for description. the figure shows waveform for either a transmitter output (sdn_tx and sdn_tx ) or a receiver input (sdn_rx and sdn_rx ). each signal swings between a volts and b volts where a > b. using this waveform, the definitions are as follows. to simplify illustration, the following definitions assume that the serdes transmitter and receiver opera te in a fully symmetrical differential signaling environment. 1. single-ended swing the transmitter output signals and the receiver input signals sdn_tx, sdn_tx , sdn_rx and sdn_rx each have a peak-to-peak swing of a - b volts. this is also referred as each signal wire?s single-ended swing. 2. differential output voltage, v od (or differential output swing ): the differential output voltage (or swing) of the transmitter, v od , is defined as the difference of the two complimentary output voltages: v sdn_tx - v sdn_tx . the v od value can be either positive or negative. 3. differential input voltage, v id (or differential input swing ): clk output delay t pckhov high-impedance t pckhoz output
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 68 freescale semiconductor high-speed serial interfaces (hssi) the differential input voltage (or swing) of the receiver, v id , is defined as the difference of the two complimentary input voltages: v sdn_rx - v sdn_rx . the v id value can be either positive or negative. 4. differential peak voltage , v diffp the peak value of the differential transmitter output signal or the differential receiver input signal is defined as differential peak voltage, v diffp = |a - b| volts. 5. differential peak-to-peak , v diffp-p since the differential output signal of the transmitter and the differential input signal of the receiver each range from a - b to -(a - b) volts, the peak-to-peak value of the differential transmitter output signal or the differential receiver input signal is defined as differential peak-to-peak voltage, v diffp-p = 2*v diffp = 2 * |(a - b)| volts, which is twice of differential swing in amplitude, or twice of the differential peak. for example, the output differential peak-peak voltage can also be calculated as v tx-diffp-p = 2*|v od |. 6. differential waveform the differential waveform is constructed by subtracting the inverting signal (sdn_tx , for example) from the non-inverting signal (sdn_tx, fo r example) within a differential pair. there is only one signal trace curve in a differential waveform. the voltage represented in the differential waveform is not referenced to ground. refer to figure 44 as an example for differential waveform. 7. common mode voltage, v cm the common mode voltage is equal to one half of the sum of the voltages between each conductor of a balanced interchange circuit and ground. in this example, for serdes output, v cm_out = v sdn_tx + v sdn_tx = (a + b) / 2, which is the arithmetic mean of the two complimentary output voltages within a differential pair. in a system , the common mode voltage may often differ from one component?s output to the other?s input. so metimes, it may be even different between the receiver input and driver output circuits within th e same component. it?s also referred as the dc offset in some occasion. figure 44. differential voltage definitions for transmitter or receiver differential swing, v id or v od = a - b a volts b volts sdn_tx or sdn_rx sdn_tx or sdn_rx differential peak voltage, v diffp = |a - b| differential peak-peak voltage, v diffpp = 2*v diffp (not shown) v cm = (a + b) / 2
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 freescale semiconductor 69 high-speed serial interfaces (hssi) to illustrate these definitions using real values, consider the case of a cml (current mode logic) transmitter that has a common mode voltage of 2.25 v and each of its outputs, td and td , has a swing that goes between 2.5v and 2.0v. using these values, the peak-to-peak voltage swing of each signal (td or td ) is 500 mv p-p, which is referred as the single-ended swing for each signal. in this example, since the differential signaling environment is fully symmetrical, the transmitter output?s differential swing (v od ) has the same amplitude as each signal?s single-ended swing. the differential output signal ranges between 500 mv and ?500 mv, in other words, v od is 500 mv in one phase and ?500 mv in the other phase. the peak differential voltage (v diffp ) is 500 mv. the peak-to-peak differential voltage (v diffp-p ) is 1000 mv p-p. 16.2 serdes reference clocks the serdes reference clock inputs are applied to an internal pll whose output creates the clock used by the corresponding serdes lanes. the serdes reference clocks inputs are sd1_ref_clk and sd1_ref_clk for pci express1 pci express2. sd2_ref_clk and sd2_ref_clk for the pci express3 or sgmii interface respectively. the following sections describe the serdes reference clock requirements and some application information.
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 70 freescale semiconductor high-speed serial interfaces (hssi) 16.2.1 serdes reference clock receiver characteristics figure 45 shows a receiver reference diagram of the serdes reference clocks. ? the supply voltage requirements for xv dd_srds2 are specified in table 1 and table 2 . ? serdes reference clock receiver reference circuit structure ? the sdn_ref_clk and sdn_ref_clk are internally ac-coupled differential inputs as shown in figure 45 . each differential clock input (sdn_ref_clk or sdn_ref_clk ) has a 50- termination to sgnd_srdsn (xcorevss) followed by on-chip ac-coupling. ? the external reference clock driver must be able to drive this termination. ? the serdes reference clock input can be eith er differential or single-ended. refer to the differential mode and single-ended mode descri ption below for further detailed requirements. ? the maximum average current requirement that also determines the common mode voltage range ? when the serdes reference clock differential i nputs are dc coupled externally with the clock driver chip, the maximum average current allowed for each input pin is 8ma. in this case, the exact common mode input voltage is not critical as long as it is within the range allowed by the maximum average current of 8 ma (refer to th e following bullet for more detail), since the input is ac-coupled on-chip. ? this current limitation sets the maximum common m ode input voltage to be less than 0.4v (0.4v/50 = 8ma) while the minimum common m ode input level is 0. 1v above sgnd_srdsn (xcorevss). for example, a clock with a 50/50 dut y cycle can be produced by a clock driver with output driven by its current source from 0ma to 16ma (0-0.8v), such that each phase of the differential input has a single-ended swing fro m 0v to 800mv with the common mode voltage at 400mv. ? if the device driving the sdn_ref_clk and sdn_ref_clk inputs cannot drive 50 ohms to sgnd_srdsn (xcorevss) dc, or it exceeds the maximum input current limitations, then it must be ac-coupled off-chip. ? the input amplitude requirement ? this requirement is described in detail in the following sections. figure 45. receiver of serdes reference clocks input amp 50 50 sdn_ref_clk sdn_ref_clk
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 freescale semiconductor 71 high-speed serial interfaces (hssi) 16.2.2 dc level requirement for serdes reference clocks the dc level requirement for the mpc8544e serdes reference clock inputs is different depending on the signaling mode used to connect the clock driver ch ip and serdes reference clock inputs as described below. ? differential mode ? the input amplitude of the differential cloc k must be between 400mv and 1600mv differential peak-peak (or between 200mv and 800mv differentia l peak). in other words, each signal wire of the differential pair must have a single- ended swing less than 800mv and greater than 200mv. this requirement is the same for both external dc-coupled or ac-coupled connection. ? for external dc-coupled connection, as described in section 16.2.1 , the maximum average current requirements sets the requirement for average voltage (common mode voltage) to be between 100 mv and 400 mv. figure 46 shows the serdes reference clock input requirement for dc-coupled connection scheme. ? for external ac-coupled connection, there is no common m ode voltage requirement for the clock driver. since the external ac-coupling capac itor blocks the dc level, the clock driver and the serdes reference clock receiver operate in different command mode voltages. the serdes reference clock receiver in this connec tion scheme has its common mode voltage set to sgnd_srdsn. each signal wire of the differential inputs is allowed to swing below and above the command mode voltage (sgnd_srdsn). figure 47 shows the serdes reference clock input requirement for ac-coupled connection scheme. ? single-ended mode ? the reference clock can also be single-ended. the sdn_ref_clk input amplitude (single-ended swing) must be between 400mv and 800mv peak-peak (from vmin to vmax) with sdn_ref_clk either left unconnected or tied to ground. ? the sdn_ref_clk input average voltage must be between 200 and 400 mv. figure 48 shows the serdes reference clock input requirement for single-ended signaling mode. ? to meet the input amplitude requirement, the re ference clock inputs might need to be dc or ac-coupled externally. for the best noise performance, the reference of the clock could be dc or ac-coupled into the unused phase (sdn_ref_clk ) through the same source impedance as the clock input (sdn_ref_clk) in use.
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 72 freescale semiconductor high-speed serial interfaces (hssi) figure 46. differential reference clock input dc requirements (external dc-coupled) figure 47. differential reference clock input dc requirements (external ac-coupled) figure 48. single-ended reference clock input dc requirements sdn_ref_clk sdn_ref_clk vmax < 800mv vmin > 0v 100mv < vcm < 400mv 200mv < input amplitude or differential peak < 800mv sdn_ref_clk sdn_ref_clk vcm 200mv < input amplitude or differential peak < 800mv vmax < vcm + 400mv vmin > vcm ? 400mv sdn_ref_clk sdn_ref_clk 400mv < sdn_ref_clk input amplitude < 800mv 0v
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 freescale semiconductor 73 high-speed serial interfaces (hssi) 16.2.3 interfacing with other differential signaling levels ? with on-chip termination to sgnd_srdsn (xcorevss), the differential reference clocks inputs are hcsl (high-speed current steering logic) compatible dc-coupled. ? many other low voltage differential type outputs like lvds (low voltage differential signaling) can be used but may need to be ac-coupled due to the limited common mode input range allowed (100 to 400 mv) for dc-coupled connection. ? lvpecl outputs can produce signal with too larg e amplitude and may need to be dc-biased at clock driver output first, then followed with series attenuation resistor to reduce the amplitude, in addition to ac-coupling. note figure 49 to figure 52 below are for conceptual reference only. due to the fact that clock driver chip's internal structure, output impedance and termination requirements are different between various clock driver chip manufacturers, it?s very possible that the clock circuit reference designs provided by clock driver chip vendor are different from what is shown below. they might also vary from one vendor to the other. therefore, freescale semiconductor can neither provide the optimal clock driver reference circuits, nor guarantee the correctness of the following clock driver connection reference circuits. the system designer is recommended to contact the selected clock driver chip vendor for the optimal reference circuits with the mpc8544e serdes reference clock receiver requirement provided in this document.
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 74 freescale semiconductor high-speed serial interfaces (hssi) figure 49 shows the serdes reference clock connection reference circuits for hcsl type clock driver. it assumes that the dc levels of the clock driver chip is compatible with mpc8544e serdes reference clock input?s dc requirement. figure 49. dc-coupled differential connection with hcsl clock driver (reference only) figure 50 shows the serdes reference clock connection reference circuits for lvds type clock driver. since lvds clock driver?s common mode voltage is higher than the mpc8544eserdes reference clock input?s allowed range (100 to 400mv), ac-coupled connection scheme must be used. it assumes the lvds output driver features 50- termination resistor. it also assumes that the lvds transmitter establishes its own common mode level without rely ing on the receiver or other external component. figure 50. ac-coupled differential connection with lvds clock driver (reference only) 50 50 sdn_ref_clk sdn_ref_clk clock driver 100 differential pwb trace clock driver vendor dependent source termination resistor serdes refer. clk receiver clock driver clk_out clk_out hcsl clk driver chip 33 33 total 50 . assume clock driver?s output impedance is about 16 . clk_out mpc8544e 50 50 sdn_ref_clk sdn_ref_clk clock driver 100 differential pwb trace serdes refer. clk receiver clock driver clk_out clk_out lvds clk driver chip 10 nf 10 nf mpc8544e
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 freescale semiconductor 75 high-speed serial interfaces (hssi) figure 51 shows the serdes reference clock connection refe rence circuits for lvpecl type clock driver. since lvpecl driver?s dc levels (both common mode voltages and output swing) are incompatible with mpc8544e serdes reference clock input?s dc requirement, ac-coupling has to be used. figure 51 assumes that the lvpecl clock driver?s output impedance is 50 . r1 is used to dc-bias the lvpecl outputs prior to ac-coupling. its value could be ranged from 140 to 240 depending on clock driver vendor?s requirement. r2 is used together with the serdes reference clock receiver?s 50- termination resistor to attenuate the lvpecl output?s differential peak level such that it meets the mpc8544e serdes reference clock?s differential input amplitude require ment (between 200mv and 800mv differential peak). for example, if the lvpecl output?s differential peak is 900mv and the desired serdes reference clock input amplitude is selected as 600mv, the atte nuation factor is 0.67, which requires r2 = 25 . please consult clock driver chip manufacturer to verify wh ether this connection scheme is compatible with a particular clock driver chip. figure 51. ac-coupled differential connection with lvpecl clock driver (reference only) 50 50 sdn_ref_clk sdn_ref_clk clock driver 100 differential pwb trace serdes refer. clk receiver clock driver clk_out clk_out lvpecl clk driver chip r2 r2 r1 r1 10nf 10nf 10nf mpc8544e
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 76 freescale semiconductor high-speed serial interfaces (hssi) figure 52 shows the serdes reference clock connection refe rence circuits for a single-ended clock driver. it assumes the dc levels of the clock driver are compatible with mpc8544e serdes reference clock input?s dc requirement. figure 52. single-ended connection (reference only) 16.2.4 ac requirements for serdes reference clocks the clock driver selected should provide a high quality reference clock with low phase noise and cycle-to-cycle jitter. phase noise less than 100khz can be tracked by the pll and data recovery loops and is less of a problem. phase noise above 15mhz is f iltered by the pll. the most problematic phase noise occurs in the 1-15mhz range. the source impedance of the clock driver should be 50 ohms to match the transmission line and reduce reflections which are a source of noise to the system. table 58 describes some ac parameters common to sgmi i, pci express and serial rapidio protocols. table 58. serdes reference clock common ac parameters at recommended operating conditions with xv dd_srds1 or xv dd_srds2 = 1.1v 5%. parameter symbol min max unit notes rising edge rate rise edge rate 1.0 4.0 v/ns 2, 3 falling edge rate fall edge rate 1.0 4.0 v/ns 2, 3 differential input high voltage v ih +200 mv 2 differential input low voltage v il -200 mv 2 50 50 sdn_ref_clk sdn_ref_clk 100 differential pwb trace serdes refer. clk receiver clock driver clk_out single-ended clk driver chip 33 total 50 . assume clock driver?s output impedance is about 16 . 50 mpc8544e
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 freescale semiconductor 77 high-speed serial interfaces (hssi) figure 53. differential measurement points for rise and fall time figure 54. single-ended measurement points for rise and fall time matching the other detailed ac requirements of the serdes re ference clocks is defined by each interface protocol based on application usage. refer to the following sections for detailed information: ? section 8.3.1, ? ac requirements for sgmii sd2_ref_clk and sd2_ref_clk ? rising edge rate (sdn_ref_clk) to falling edge rate (sdn_ref_clk ) matching rise-fall matching 20 % 1, 4 notes: 1. measurment taken from single ended waveform. 2. measurment taken from differential waveform. 3. measured from -200 mv to +200 mv on the differential waveform (derived from sdn_ref_clk minus sdn_ref_clk ). the signal must be monotonic through the measurement region for rise and fall time. the 400 mv measurement window is centered on the differential zero crossing. see figure 53 . 4. matching applies to rising edge rate for sd n_ref_clk and falling edge rate for sdn_ref_clk . it is measured using a 200 mv window centered on the median cross point where sdn_ref_clk rising meets sdn_ref_clk falling. the median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. the rise edge rate of sdn_ref_clk should be compared to the fall edge rate of sdn_ref_clk , the maximum allowed difference should not exceed 20% of the slowest edge rate. see figure 54 . table 58. serdes reference clock common ac parameters (continued) at recommended operating conditions with xv dd_srds1 or xv dd_srds2 = 1.1v 5%. parameter symbol min max unit notes v ih = +200 v il = -200 mv 0.0 v sdn_ref_cl k minus sdn_ref_clk sdn_ref_clk sdn_ref_clk sdn_ref_clk
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 78 freescale semiconductor pci express ? section 17.2, ?ac requirements for pci express serdes clocks? 16.2.4.1 spread spectrum clock sd1_ref_clk/sd1_ref_clk were designed to work with a spread spectrum clock (+0 to -0.5% spreading at 30?33 khz rate is allowed), assuming both e nds have same reference clock. for better results, a source without significant unintended modulation should be used. sd2_ref_clk/sd2_ref_clk are not intended to be used with, and should not be clocked by, a spread spectrum clock source. 16.3 serdes transmitter and receiver reference circuits figure 55 shows the reference circuits for serdes data lane?s transmitter and receiver. figure 55. serdes transmitter and receiver reference circuits the dc and ac specification of serdes data lanes are defined in section below (pci express, or sgmii) in this document based on the application usage: ? section 8.3, ?sgmii interface electrical characteristics ? section 17, ?pci express please note that external ac coupling capacitor is required for the above serial transmission protocols with the capacitor value defined in specification of each protocol section. 17 pci express this section describes the dc and ac electrical specifications for the pci express bus of the mpc8544. 17.1 dc requirements for pci express sd_ref_clk and sd_ref_clk for more information, see section 16.1, ?dc requirements for serdes reference clocks.? 50 50 receiver transmitter sd1_tx n or sd2_tx n sd1_txn or sd2_txn sd1_rxn or sd2_rxn sd1_rx n or sd2_rx n 50 50
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 freescale semiconductor 79 pci express 17.2 ac requirements for pci express serdes clocks table 59 provides the ac requirements for the pci express serdes clocks. 17.3 clocking dependencies the ports on the two ends of a link must transmit data at a rate that is within 600 parts per million (ppm) of each other at all times. this is specified to a llow bit rate clock sources with a 300 ppm tolerance. 17.4 physical layer specifications the following is a summary of the specifications for the physical layer of pci express on this device. for further details as well as the specifications of the transport and data link layer please refer to the pci express base specification . rev. 1.0a . 17.4.1 differential transmitter (tx) output table 60 defines the specifications for the differential output at all transmitters (txs). the parameters are specified at the component pins. table 59. sd_ref_clk and sd_ref_clk ac requirements symbol 2 parameter description min typical max units notes t ref refclk cycle time ? 10 ? ns 1 t refcj refclk cycle-to-cycle jitter. difference in the period of any two adjacent refclk cycles ??100ps t refpj phase jitter. deviation in edge location with respect to mean edge location ?50 ? 50 ps notes: 1. typical based on pci express specification 2.0 . 2. guaranteed by characterization. table 60. differential transmitter (tx) output specifications symbol parameter min nom max units comments ui unit interval 399.88 400 400.12 ps each ui is 400 ps 300 ppm. ui does not account for spread spectrum clock dictated variations. see note 1. v tx-diffp-p differential peak-to- peak output voltage 0.8 1.2 v v tx-diffp-p = 2*|v tx-d+ ? v tx-d? |. see note 2. v tx-de-ratio de- emphasized differential output voltage (ratio) ?3.0 ?3.5 ?4.0 db ratio of the v tx-diffp-p of the second and following bits after a transition divided by the v tx-diffp-p of the first bit after a transition. see note 2. t tx-eye minimum tx eye width 0.70 ui the maximum transmitter jitter can be derived as t tx-max-jitter = 1 ? t tx-eye = 0.3 ui. see notes 2 and 3.
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 80 freescale semiconductor pci express t tx-eye-median-to- max-jitter maximum time between the jitter median and maximum deviation from the median. 0.15 ui jitter is defined as the measurement variation of the crossing points (v tx-diffp-p = 0 v) in relation to a recovered tx ui. a recovered tx ui is calculated over 3500 consecutive unit intervals of sample data. jitter is measured using all edges of the 250 consecutive ui in the center of the 3500 ui used for calculating the tx ui. see notes 2 and 3. t tx-rise , t tx-fall d+/d? tx output rise/fall time 0.125 ui see notes 2 and 5. v tx-cm-acp rms ac peak common mode output voltage 20 mv v tx-cm-acp = rms(|v txd+ ? v txd? |/2 ? v tx-cm-dc ) v tx-cm-dc = dc (avg) of |v tx-d+ ? v tx-d? |/2 see note 2. v tx-cm-dc-active- idle-delta absolute delta of dc common mode voltage during lo and electrical idle 0100mv|v tx-cm-dc (during lo) ? v tx-cm-idle-dc (during electrical idle) |<= 100 mv v tx-cm-dc = dc (avg) of |v tx-d+ ? v tx-d? |/2 [lo] v tx-cm-idle-dc = dc (avg) of |v tx-d+ ? v tx-d? |/2 [electrical idle] see note 2. v tx-cm-dc-line-delta absolute delta of dc common mode between d+ and d? 025mv|v tx-cm-dc-d+ ? v tx-cm-dc-d? | <= 25 mv v tx-cm-dc-d+ = dc (avg) of |v tx-d+ | v tx-cm-dc-d? = dc (avg) of |v tx-d? | see note 2. v tx-idle-diffp electrical idle differential peak output voltage 020mvv tx-idle-diffp = |v tx-idle-d+ ? v tx-idle-d? | <= 20 mv see note 2. v tx-rcv-detect amount of voltage change allowed during receiver detection 600 mv the total amount of voltage change that a transmitter can apply to sense whether a low impedance receiver is present. see note 6. v tx-dc-cm tx dc common mode voltage 0 3.6 v the allowed dc common mode voltage under any conditions. see note 6. i tx-short tx short circuit current limit 90 ma the total current the transmitter can provide when shorted to its ground. t tx-idle-min minimum time spent in electrical idle 50 ui minimum time a transmitter must be in electrical idle utilized by the receiver to start looking for an electrical idle exit after successfully receiving an electrical idle ordered set. table 60. differential transmitter (tx) output specifications (continued) symbol parameter min nom max units comments
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 freescale semiconductor 81 pci express t tx-idle-set-to-idle maximum time to transition to a valid electrical idle after sending an electrical idle ordered set 20 ui after sending an electrical idle ordered set, the transmitter must meet all electrical idle specifications within this time. this is considered a debounce time for the transmitter to meet electrical idle after transitioning from lo. t tx-idle-to-diff-data maximum time to transition to valid tx specifications after leaving an electrical idle condition 20 ui maximum time to meet all tx specifications when transitioning from electrical idle to sending differential data. this is considered a debounce time for the tx to meet all tx specifications after leaving electrical idle. rl tx-diff differential return loss 12 db measured over 50 mhz to 1.25 ghz. see note 4. rl tx-cm common mode return loss 6 db measured over 50 mhz to 1.25 ghz. see note 4. z tx-diff-dc dc differential tx impedance 80 100 120 tx dc differential mode low impedance. z tx-dc transmitter dc impedance 40 required tx d+ as well as d? dc impedance during all states. l tx-skew lane-to-lane output skew 500 + 2 ui ps static skew between any two transmitter lanes within a single link. c tx ac coupling capacitor 75 200 nf all transmitters shall be ac coupled. the ac coupling is required either within the media or within the transmitting component itself. table 60. differential transmitter (tx) output specifications (continued) symbol parameter min nom max units comments
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 82 freescale semiconductor pci express 17.4.2 transmitter compliance eye diagrams the tx eye diagram in figure 56 is specified using the passive compliance/test measurement load (see figure 58 ) in place of any real pci express interconnect +rx component. there are two eye diagrams that must be met for the transmitter. both eye diagrams must be aligned in time using the jitter median to locate the center of the eye diagram. the different eye diagrams will differ in voltage depending whether it is a transition bit or a de-emphasized bit. the exact reduced voltage level of the de-emphasized bit will always be relative to the transition bit. the eye diagram must be valid for any 250 consecutive uis. a recovered tx ui is calculated over 3500 consecutive un it intervals of sample data. the eye diagram is created using all edges of the 250 consecutive ui in the center of the 3500 ui used for calculating the tx ui. note it is recommended that the recovered tx ui is calculated using all edges in the 3500 consecutive ui interval with a fit algorithm using a minimization merit function (that is, least squa res and median deviation fits). t crosslink crosslink random timeout 0 1 ms this random timeout helps resolve conflicts in crosslink configuration by eventually resulting in only one downstream and one upstream port. see note 7. notes: 1.)no test load is necessarily associated with this value. 2.)specified at the measurement point into a timing and voltage compliance test load as shown in figure 58 and measured over any 250 consecutive tx uis. (also refer to the transmitter compliance eye diagram shown in figure 56 .) 3.)a t tx-eye = 0.70 ui provides for a total sum of deterministic and random jitter budget of t tx-jitter-max = 0.30 ui for the transmitter collected over any 250 consecutive tx uis. the t tx-eye-median-to-max-jitter median is less than half of the total tx jitter budget collected over any 250 consecutive tx uis. it should be noted that the median is not the same as the mean. the jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed to the averaged time value. 4.)the transmitter input impedance shall result in a differential return loss greater than or equal to 12 db and a common mode return loss greater than or equal to 6 db over a frequency range of 50 mhz to 1.25 ghz. this input impedance requirement applies to all valid input levels. the reference impedance for return loss measurements is 50 to ground for both the d+ and d? line (that is, as measured by a vector network analyzer with 50- probes?see figure 58 ). note that the series capacitors c tx is optional for the return loss measurement. 5.)measured between 20%?80% at transmitter package pins into a test load as shown in figure 58 for both v tx-d+ and v tx-d? . 6.)see section 4.3.1.8 of the pci express base specifications, rev 1.0a. 7.)see section 4.2.6.3 of the pci express base specifications, rev 1.0a. table 60. differential transmitter (tx) output specifications (continued) symbol parameter min nom max units comments
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 freescale semiconductor 83 pci express figure 56. minimum transmitter timing and voltage output compliance specifications 17.4.3 differential receiver (rx) input specifications table 61 defines the specifications for the differential i nput at all receivers (rxs). the parameters are specified at the component pins. table 61. differential receiver (rx) input specifications symbol parameter min nom max units comments ui unit interval 399.88 400 400.12 ps each ui is 400 ps 300 ppm. ui does not account for spread spectrum clock dictated variations. see note 1. v rx-diffp-p differential peak-to- peak input voltage 0.175 1.200 v v rx-diffp-p = 2*|v rx-d+ ? v rx-d? | see note 2. t rx-eye minimum receiver eye width 0.4 ui the maximum interconnect media and transmitter jitter that can be tolerated by the receiver can be derived as t rx-max-jitter = 1 ? t rx-eye = 0.6 ui. see notes 2 and 3.
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 84 freescale semiconductor pci express t rx-eye-median-to-max -jitter maximum time between the jitter median and maximum deviation from the median 0.3 ui jitter is defined as the measurement variation of the crossing points (v rx-diffp-p = 0 v) in relation to a recovered tx ui. a recovered tx ui is calculated over 3500 consecutive unit intervals of sample data. jitter is measured using all edges of the 250 consecutive ui in the center of the 3500 ui used for calculating the tx ui. see notes 2, 3, and 7. v rx-cm-acp ac peak common mode input voltage 150 mv v rx-cm-acp = |v rxd+ ? v rxd? |/2 ? v rx-cm-dc v rx-cm-dc = dc (avg) of |v rx-d+ ? v rx-d? |/2 see note 2. rl rx-diff differential return loss 15 db measured over 50 mhz to 1.25 ghz with the d+ and d? lines biased at +300 and ?300 mv, respectively. see note 4. rl rx-cm common mode return loss 6 db measured over 50 mhz to 1.25 ghz with the d+ and d? lines biased at 0 v. see note 4. z rx-diff-dc dc differential input impedance 80 100 120 rx dc differential mode impedance. see note 5. z rx-dc dc input impedance 40 50 60 required rx d+ as well as d? dc impedance (50 20% tolerance). see notes 2 and 5. z rx-high-imp-dc powered down dc input impedance 200 k required rx d+ as well as d? dc impedance when the receiver terminations do not have power. see note 6. v rx-idle-det-diffp-p electrical idle detect threshold 65 175 mv v rx-idle-det-diffp-p = 2*|v rx-d+ ? v rx-d? | measured at the package pins of the receiver. t rx-idle-det-diff- entertime unexpected electrical idle enter detect threshold integration time 10 ms an unexpected electrical idle (v rx-diffp-p < v rx-idle-det-diffp-p ) must be recognized no longer than t rx-idle-det-diff-entering to signal an unexpected idle condition. table 61. differential receiver (rx) input specifications (continued) symbol parameter min nom max units comments
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 freescale semiconductor 85 pci express 17.5 receiver compliance eye diagrams the rx eye diagram in figure 57 is specified using the passive compliance/test measurement load (see figure 58 ) in place of any real pci express rx component. in general, the minimum receiver eye diagram measured with the compliance/test measurement load (see figure 58 ) will be larger than the minimum receiver eye diagram measured over a range of systems at the input receiver of any real pci express component. th e degraded eye diagram at the input receiver is due to traces internal to the package as well as silicon parasitic characteristics which cause the real pci express component to vary in impedance from the complian ce/test measurement load . the input receiver eye diagram is implementation specific and is not specifie d. rx component designer should provide additional margin to adequately compensate for the degraded minimum receiver eye diagram (shown in figure 57 ) expected at the input receiver based on some adequate combination of system simulations and the return loss measured looking into the rx package and silicon. the rx eye diagram must be aligned in time using the jitter median to locate the center of the eye diagram. l tx-skew total skew 20 ns skew across all lanes on a link. this includes variation in the length of skp ordered set (for example, com and one to five symbols) at the rx as well as any delay differences arising from the interconnect itself. notes: 1.)no test load is necessarily associated with this value. 2.)specified at the measurement point and measured over any 250 consecutive uis. the test load in figure 58 should be used as the rx device when taking measurements (also refer to the receiver compliance eye diagram shown in figure 57 ). if the clocks to the rx and tx are not derived from the same reference clock, the tx ui recovered from 3500 consecutive ui must be used as a reference for the eye diagram. 3.)a t rx-eye = 0.40 ui provides for a total sum of 0.60 ui deterministic and random jitter budget for the transmitter and interconnect collected any 250 consecutive uis. the trx-eye-median-to-max-jitter specification ensures a jitter distribution in which the median and the maximum deviation from the median is less than half of the total. ui jitter budget collected over any 250 consecutive tx uis. it should be noted that the median is not the same as the mean. the jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed to the averaged time value. if the clocks to the rx and tx are not derived from the same reference clock, the tx ui recovered from 3500 consecutive ui must be used as the reference for the eye diagram. 4.)the receiver input impedance shall result in a differential return loss greater than or equal to 15 db with the d+ line bias ed to 300 mv and the d? line biased to ?300 mv and a common mode return loss greater than or equal to 6 db (no bias required) over a frequency range of 50 mhz to 1.25 ghz. this input impedance requirement applies to all valid input levels. the reference impedance for return loss measurements for is 50 to ground for both the d+ and d? line (that is, as measured by a vector network analyzer with 50- probes, see figure 58 ). note that the series capacitors ctx is optional for the return loss measurement. 5.)impedance during all ltssm states. when transitioning from a fundamental reset to detect (the initial state of the ltssm) there is a 5-ms transition time before receiver termination values must be met on all unconfigured lanes of a port. 6.)the rx dc common mode impedance that exists when no power is present or fundamental reset is asserted. this helps ensure that the receiver detect circuit will not falsely assume a receiver is powered on when it is not. this term must be measured at 300 mv above the rx ground. 7.)it is recommended that the recovered tx ui is calculated using all edges in the 3500 consecutive ui interval with a fit algo rithm using a minimization merit function. least squares and median deviation fits have worked well with experimental and simulated data. table 61. differential receiver (rx) input specifications (continued) symbol parameter min nom max units comments
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 86 freescale semiconductor pci express the eye diagram must be valid for any 250 consecutive uis. a recovered tx ui is calculated over 3500 consecutive un it intervals of sample data. the eye diagram is created using all edges of the 250 consecutive ui in the center of the 3500 ui used for calculating the tx ui. note the reference impedance for return loss measurements is 50 to ground for both the d+ and d? line (that is, as measured by a vector network analyzer with 50- probes, see figure 58 ). note that the series capacitors, ctx, are optional for the return loss measurement. figure 57. minimum receiver eye timing and voltage compliance specification 17.5.1 compliance test and measurement load the ac timing and voltage parameters must be verified at the measurement point, as specified within 0.2 inches of the package pins, into a test/measurement load shown in figure 58 . note the allowance of the measurement point to be within 0.2 inches of the package pins is meant to acknowledge that package/board routing may benefit from d+ and d? not being exac tly matched in length at the package pin boundary.
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 freescale semiconductor 87 package description figure 58. compliance test/measurement load 18 package description this section details package paramete rs, pin assignments, and dimensions. 18.1 package parameters for the mpc8544e fc-pbga the package parameters for flip chip plastic ball grid array (fc-pbga) are provided in table 62 . 18.2 mechanical dimensions of the mpc8544e fc-pbga figure 59 shows the mechanical dimensions and bo ttom surface nomenclature of the mpc8544e, 783 fc-pbga package without a lid. table 62. package parameters parameter pbga 1 package outline 29 mm 29 mm interconnects 783 ball pitch 1 mm ball diameter (typical) 0.6 mm solder ball (pb-free) 95.5% sn 3.5% ag note : 1. (fc-pbga) without a lid.
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 88 freescale semiconductor package description figure 59. mechanical dimensions and bottom surface nomenclature of the mpc8544e fc-pbga without a lid notes: 1. all dimensions are in millimeters. 2. dimensions and tolerances per asme y14.5m-1994. 3. maximum solder ball diameter measured parallel to datum a. 4. datum a, the seating plane, is determined by the spherical crowns of the solder balls. 5. parallelism measurement shall exclude any effect of mark on top surface of package. 6. capacitors may not be present on all parts. care must be taken not to short exposed metal capacitor pads. 7. all dimensions are symmetric across the package center lines, unless dimensioned otherwise.
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 freescale semiconductor 89 package description 18.3 pinout listings note the naming convention of tsec1 and tsec3 is used to allow the splitting voltage rails for the etsec blocks and to ease the port of existing powerquicc iii software. note the dma_dack [0:1] and test_sel pins must be set to a proper state during por configuration. please refer to table 63 for more details. table 63 provides the pinout listing for the mpc8544e 783 fc-pbga package. table 63. mpc8544epinout listing signal package pin number pin type power supply notes pci pci1_ad[31:0] ae8, ad8, af8, ah12, ag12, ab9, ac9, ae9, ad10, ae10, ac11, ab11, ab12, ac12, af12, ae11, y14, ae15, ac15, ab15, aa15, ad16, y15, ab16, af18, ae18, ac17, ae19, ad19, ab17, ab18, aa16 i/o ov dd pci1_c_be [3:0] ac10, ae12, aa14, ad17 i/o ov dd pci1_gnt [4:1] ae7, ag11,ah11, ac8 o ov dd 4, 8, 24 pci1_gnt0 ae6 i/o ov dd pci1_irdy af13 i/o ov dd 2 pci1_par ab14 i/o ov dd pci1_perr ae14 i/o ov dd 2 pci1_serr ac14 i/o ov dd 2 pci1_stop aa13 i/o ov dd 2 pci1_trdy ad13 i/o ov dd 2 pci1_req [4:1] af9, ag10, ah10, ad6 i ov dd pci1_req0 ab8 i/o ov dd pci1_clk ah26 i ov dd pci1_devsel ac13 i/o ov dd 2 pci1_frame ad12 i/o ov dd 2 pci1_idsel ag6 i ov dd
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 90 freescale semiconductor package description ddr sdram memory interface mdq[0:63] a26, b26, c22, d21, d25, b25, d22, e21, a24, a23, b20, a20, a25, b24, b21, a21, e19, d19, e16, c16, f19, f18, f17, d16, b18, a18, a15, b14, b19, a19, a16, b15, d1, f3, g1, h2, e4, g5, h3, j4, b2, c3, f2, g2, a2, b3, e1, f1, l5, l4,n3, p3, j3, k4, n4, p4, j1, k1, p1, r1, j2, k2, n1, r2 i/o gv dd mecc[0:7] g12, d14, f11, c11, g14, f14,c13, d12 i/o gv dd mdm[0:8] c25, b23, d18, b17, g4, c2, l3, l2, f13 o gv dd 21 mdqs [0:8] d24, b22, c18, a17, j5, c1, m4, m2, e13 i/o gv dd mdqs[0:8] c23, a22, e17, b16, k5, d2, m3, p2, d13 i/o gv dd ma[0:15] b7, g8, c8, a10, d9, c10, a11, f9, e9, b12, a5, a12, d11, f7, e10, f10 ogv dd mba[0:2] a4, b5, b13 o gv dd mwe b4 o gv dd mcas e7 o gv dd mras c5 o gv dd mcke[0:3] h10, k10, g10, h9 o gv dd 10 mcs [0:3] d3, h6, c4, g6 o gv dd mck[0:5] a9, j11, j6, a8, j13, h8 o gv dd mck [0:5] b9, h11, k6, b8, h13, j8 o gv dd modt[0:3] e5, h7, e6, f6 o gv dd mdic[0:1] h15, k15 i/o gv dd 25 test_in a13 i 27 test_out a6 o 17 local bus controller interface lad[0:31] k22, l21, l22, k23, k24, l24, l25, k25, l28, l27, k28, k27, j28, h28, h27, g27, g26, f28, f26, f25, e28, e27, e26, f24, e24, c26, g24, e23, g23, f22, g22, g21 i/o bv dd 23 ldp[0:3] k26, g28, b27, e25 i/o bv dd la[27] l19 o bv dd 4, 8 la[28:31] k16, k17, h17,g17 o bv dd 4, 6, 8 lcs [0:4] k18, g19, h19, h20, g16 o bv dd lcs5 /dma_dreq2 h16 i/o bv dd 1 table 63. mpc8544epinout listing (continued) signal package pin number pin type power supply notes
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 freescale semiconductor 91 package description lcs6 /dma_dack2 j16 o bv dd 1 lcs7 /dma_ddone2 l18 o bv dd 1 lwe0 /lbs0/ lsddqm[0] j22 o bv dd 4, 8 lwe1 /lbs1/ lsddqm[1] h22 o bv dd 4, 8 lwe2 /lbs2/ lsddqm[2] h23 o bv dd 4, 8 lwe3 /lbs3/ lsddqm[3] h21 o bv dd 4, 8 lale j26 o bv dd 4, 7, 8 lbctl j25 o bv dd 4, 7, 8 lgpl0/lsda10 j20 o bv dd 4, 8 lgpl1/lsdwe k20 o bv dd 4, 8 lgpl2/loe /lsdras g20 o bv dd 4, 7, 8 lgpl3/lsdcas h18 o bv dd 4, 8 lgpl4/lgta /lupwait/ lpbse l20 i/o bv dd lgpl5 k19 o bv dd 4, 8 lcke l17 o bv dd lclk[0:2] h24, j24, h25 o bv dd lsync_in d27 i bv dd lsync_out d28 o bv dd dma dma_dack [0:1] y13, y12 o ov dd 4, 8, 9 dma_dreq [0:1] aa10, aa11 i ov dd dma_ddone [0:1] aa7, y11 o ov dd programmable interrupt controller ude ah15 i ov dd mcp ag18 i ov dd irq[0:7] ag22, af17, ad21, af19, ag17, af16, ac23, ac22 iov dd irq[8] ac19 i ov dd irq[9]/dma_dreq3 ag20 i ov dd 1 irq[10]/dma_dack3 ae27 i/o ov dd 1 irq[11]/dma_ddone3 ae24 i/o ov dd 1 irq_out ad14 o ov dd 2 table 63. mpc8544epinout listing (continued) signal package pin number pin type power supply notes
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 92 freescale semiconductor package description ethernet management interface ec_mdc ac7 o ov dd 4, 8, 14 ec_mdio y9 i/o ov dd gigabit reference clock ec_gtx_clk125 t2 i lv dd three-speed ethernet controller (gigabit ethernet 1) tsec1_rxd[7:0] u10, u9, t10, t9, u8, t8, t7, t6 i lv dd tsec1_txd[7:0] t5, u5, v5, v3, v2, v1, u2, u1 o lv dd 4, 8, 14 tsec1_col r5 i lv dd tsec1_crs t4 i/o lv dd 16 tsec1_gtx_clk t1 o lv dd tsec1_rx_clk v7 i lv dd tsec1_rx_dv u7 i lv dd tsec1_rx_er r9 i lv dd 4, 8 tsec1_tx_clk v6 i lv dd tsec1_tx_en u4 o lv dd 22 tsec1_tx_er t3 o lv dd three-speed ethernet controller (gigabit ethernet 3) tsec3_rxd[7:0] p11, n11, m11, l11, r8, n10, n9, p10 i lv dd tsec3_txd[7:0] m7, n7, p7, m8, l7, r6, p6, m6 o lv dd 4, 8, 14 tsec3_col m9 i lv dd tsec3_crs l9 i/o lv dd 16 tsec3_gtx_clk r7 o lv dd tsec3_rx_clk p9 i lv dd tsec3_rx_dv p8 i lv dd tsec3_rx_er r11 i lv dd tsec3_tx_clk l10 i lv dd tsec3_tx_en n6 o lv dd 22 tsec3_tx_er l8 o lv dd 4, 8 duart uart_cts [0:1] ah8, af6 i ov dd uart_rts [0:1] ag8, ag9 o ov dd table 63. mpc8544epinout listing (continued) signal package pin number pin type power supply notes
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 freescale semiconductor 93 package description uart_sin[0:1] ag7, ah6 i ov dd uart_sout[0:1] ah7, af7 o ov dd i 2 c interface iic1_scl ag21 i/o ov dd 20 iic1_sda ah21 i/o ov dd 20 iic2_scl ag13 i/o ov dd 20 iic2_sda ag14 i/o ov dd 20 serdes 1 sd1_rx[0:7] n28, p26, r28, t26, y26, aa28, ab26, ac28 i xv dd sd1_rx [0:7] n27, p25, r27, t25, y25, aa27, ab25, ac27 i xv dd sd1_tx[0:7] m23, n21, p23, r21, u21, v23, w21, y23 o xv dd sd1_tx [0:7] m22, n20, p22, r20, u20, v22, w20, y22 o xv dd sd1_pll_tpd v28 o xv dd 17 sd1_ref_clk u28 i xv dd sd1_ref_clk u27 i xv dd sd1_tst_clk t22 sd1_tst_clk t23 serdes 2 sd2_rx[0] ad25 i xv dd sd2_rx[2] ad1 i xv dd 26 sd2_rx[3] ab2 i xv dd 26 sd2_rx [0] ad26 i xv dd sd2_rx [2] ac1 i xv dd 26 sd2_rx [3] aa2 i xv dd 26 sd2_tx[0] aa21 o xv dd sd2_tx[2] ac4 o xv dd 26 sd2_tx[3] aa5 o xv dd 26 sd2_tx [0] aa20 o xv dd sd2_tx [2] ab4 o xv dd 26 sd2_tx [3] y5 o xv dd 26 sd2_pll_tpd ag3 o xv dd 17 sd2_ref_clk ae2 i xv dd table 63. mpc8544epinout listing (continued) signal package pin number pin type power supply notes
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 94 freescale semiconductor package description sd2_ref_clk af2 i xv dd sd2_tst_clk ag4 sd2_tst_clk af4 general-purpose output gpout[0:7] af22, ah23, ag27, ah25, af21, af25, ag26, af26 oov dd general-purpose input gpin[0:7] ah24, ag24, ad23, ae21, ad22, af23, ag25, ae20 iov dd system control hreset ag16 i ov dd hreset_req ag15 o ov dd 21 sreset ag19 i ov dd ckstp_in ah5 i ov dd ckstp_out aa12 o ov dd 2, 4 debug trig_in ac5 i ov dd trig_out/ready/ quiesce ab5 o ov dd 5, 8, 15, 21 msrcid[0:1] y7, w9 o ov dd 4, 5, 8 msrcid[2:4] aa9, ab6, ad5 o ov dd 5, 15, 21 mdval y8 o ov dd 5 clk_out ae16 o ov dd 10 clock rtc af15 i ov dd sysclk ah16 i ov dd jtag tck ag28 i ov dd tdi ah28 i ov dd 11 tdo af28 o ov dd 10 tms ah27 i ov dd 11 trst ah22 i ov dd 11 table 63. mpc8544epinout listing (continued) signal package pin number pin type power supply notes
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 freescale semiconductor 95 package description dft l1_tstclk ac20 i ov dd 18 l2_tstclk ae17 i ov dd 18 lssd_mode ah19 i ov dd 18 test_sel ah13 i ov dd 3 thermal management temp_anode y3 ? 13 temp_cathode aa3 ? 13 power management asleep ah17 o ov dd 8, 15, 21 power and ground signals gnd d5, m10, f4, d26, d23, c12, c15, e20, d8, b10, e3, j14, k21, f8, a3, f16, e12, e15, d17, l1, f21, h1, g13, g15, g18, c6, a14, a7, g25, h4, c20, j12, j15, j17, f27, m5, j27, k11, l26, k7, k8, l12, l15, m14, m16, m18, n13, n15, n17, n2, p5, p14, p16, p18, r13, r15, r17, t14, t16, t18, u13, u15, u17, aa8, u6, y10, ac21, aa17, ac16, v4, ad7, ad18, ae23, af11, af14, ag23, ah9, a27, b28, c27 ?? ov dd [1:17] y16, ab7, ab10, ab13, ac6, ac18, ad9, ad11, ae13, ad15, ad20, ae5, ae22, af10, af20, af24, af27 power for pci and other standards (3.3 v) ov dd lv dd [1:2] r4, u3 power for tsec1 interfaces (2.5 v, 3.3 v) lv dd tv dd [1:2] n8, r10 power for tsec3 interfaces (2.5 v, 3.3 v) tv dd gv dd b1, b11, c7, c9, c14, c17, d4, d6, r3, d15, e2, e8,c24, e18, f5, e14, c21, g3, g7, g9, g11, h5, h12, e22, f15, j10, k3, k12, k14, h14, d20, e11, m1, n5 power for ddr1 and ddr2 dram i/o voltage (1.8 v, 2.5 v) gv dd bv dd l23, j18, j19, f20, f23, h26, j21, j23 power for local bus (1.8 v, 2.5 v, 3.3 v) bv dd table 63. mpc8544epinout listing (continued) signal package pin number pin type power supply notes
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 96 freescale semiconductor package description v dd l16, l14, m13, m15, m17, n12, n14, n16, n18, p13, p15, p17, r12, r14, r16, r18, t13, t15, t17, u12, u14, u16, u18, power for core (1.0 v) v dd svdd_srds m27, n25, p28, r24, r26, t24, t27, u25, w24, w26, y24, y27, aa25, ab28, ad27 core power for serdes 1 transceivers (1.0 v) sv dd svdd_srds2 ab1, ac26, ad2, ae26, ag2 core power for serdes 2 transceivers (1.0 v) sv dd xvdd_srds m21, n23, p20, r22, t20, u23, v21, w22, y20 pad power for serdes 1 transceivers (1.0 v) xv dd xvdd_srds2 y6, aa6, aa23, af5, ag5 pad power for serdes 2 transceivers (1.0 v) xv dd xgnd_srds m20, m24, n22, p21, r23, t21, u22, v20, w23, y21 xgnd_srds2 y4, aa4, aa22, ad4, ae4, ah4 sgnd_srds m28, n26, p24, p27, r25, t28, u24, u26, v24, w25, y28, aa24, aa26, ab24, ab27, ac24, ad28 agnd_srds v27 serdes pll gnd sgnd_srds2 y2, aa1, ab3, ac2, ac3, ac25, ad3, ad24, ae3, ae1, ae25, af3, ah2 agnd_srds2 af1 serdes pll gnd avdd_lbiu c28 power for local bus pll (1.0 v) 19 avdd_pci1 ah20 power for pci pll (1.0 v) 19 avdd_core ah14 power for e500 pll (1.0 v) 19 avdd_plat ah18 power for ccb pll (1.0 v) 19 table 63. mpc8544epinout listing (continued) signal package pin number pin type power supply notes
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 freescale semiconductor 97 package description avdd_srds w28 power for srdspll (1.0 v) 19 avdd_srds2 ag1 power for srdspll (1.0 v) 19 sensevdd w11 o v dd 12 sensevss w10 12 analog signals mvref a28 reference voltage signal for ddr mvref sd1_imp_cal_rx m26 200 to gnd sd1_imp_cal_tx ae28 100 to gnd sd1_pll_tpa v26 avdd_srds analog 17 sd2_imp_cal_rx ah3 i 200 to gnd sd2_imp_cal_tx y1 i 100 to gnd sd2_pll_tpa ah1 o avdd_srds2 analog 17 no connect pins nc c19, d7, d10, k13, l6, k9, b6, f12, j7, m19, m25, n19, n24, p19, r19, ab19, t12, w3, m12, w5, p12, t19, w1, w7, l13, u19, w4, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, w2, w6, w8, t11, u11, w12, w13, w14, w15, w16, w17, w18, w19, w27, v25, y17, y18, y19, aa18, aa19, ab20, ab21, ab22, ab23, j9 table 63. mpc8544epinout listing (continued) signal package pin number pin type power supply notes
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 98 freescale semiconductor package description notes: 1. all multiplexed signals are listed only once and do not re-occur. for example, lcs5 /dma_req2 is listed only once in the local bus controller interface section, and is not mentioned in the dma section even though the pin also functions as dma_req2 . 2. recommend a weak pull-up resistor (2?10 k ) be placed on this pin to ov dd . 3. this pin must always be pulled high. 4. this pin is a reset configuration pin. it has a weak internal pull-up p-fet which is enabled only when the processor is in th e reset state. this pull-up is designed such that it can be overpowered by an external 4.7-k pull-down resistor. however, if the signal is intended to be high after reset, and if there is any device on the net which might pull down the value of the net at reset, then a pull-up or active driver is needed. tsec3_txd[3] (cfg_srds_sgmii_refclk) is an exception, because the default value of this configuration signal is low (0). thus, no external pull-down resistor is needed for selecting the default configuration value. 5. treat these pins as no connects (nc) unless using debug address functionality. 6. the value of la[28:31] during reset sets the ccb clock to sysclk pll ratio. these pins require 4.7-k pull-up or pull-down resistors. see section 19.2, ?ccb/sysclk pll ratio.? 7. the value of lale, lgpl2, and lbctl at reset set the e500 core clock to ccb clock pll ratio. these pins require 4.7-k pull-up or pull-down resistors. see section 19.3, ?e500 core pll ratio.? 8. functionally, this pin is an output, but structurally it is an i/o because it either samples configuration input during reset or because it has other manufacturing test functions. therefore, this pin will be described as an i/o for boundary scan. 9. for proper state of these signals during reset, dma_dack [1] must be pulled down to gnd through a resistor. dma_dack [0] can be pulled up or left without a resistor. however, if there is any device on the net which might pull down the value of the net at reset, then a pullup is needed on dma_dack [0]. 10. this output is actively driven during reset rather than being three-stated during reset. 11. these jtag pins have weak internal pull-up p-fets that are always enabled. 12. these pins are connected to the v dd /gnd planes internally and may be used by the core power supply to improve tracking and regulation. 13. anode and cathode of internal thermal diode. 14. treat pins ac7, t5, v2, and m7 as spare configuration pins cfg_spare[0:3]. the spare pins are unused por config pins. it is highly recommended that the customer provide the capab ility of setting these pins low (that is, pull-down resistor which is not currently stuffed) in order to support new config options should they arise between revisions. 15. if this pin is connected to a device that pulls down during reset, an external pull-up is required to drive this pin to a sa fe state during reset. 16. this pin is only an output in fifo mode when used as rx flow control. 17. do not connect. 18. these are test signals for factory use only and must be pulled up (100 to 1 k ) to ov dd for normal machine operation. 19. independent supplies derived from board v dd . 20. recommend a pull-up resistor (1 k~) be placed on this pin to ov dd . 21. the following pins must not be pulled down during power-on reset: hreset_req , trig_out/ready/quiesce , msrcid[2:4], and asleep. 22. this pin requires an external 4.7-k pull-down resistor to prevent phy from seeing a valid transmit enable before it is actively driven. 23. general-purpose por configuration of user system. table 63. mpc8544epinout listing (continued) signal package pin number pin type power supply notes
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 freescale semiconductor 99 clocking 19 clocking this section describes the pll configuration of the mpc8544e. note that the platform clock is identical to the core complex bus (ccb) clock. 19.1 clock ranges table 64 provides the clocking specifications for the processor cores and table 65 provides the clocking specifications for the memory bus. 24. when a pci block is disabled, either the por config pin that selects between internal and external arbiter must be pulled down to select external arbiter if there is any other pci device connected on the pci bus, or leave the address pins as no connect or terminated through 2?10 k pull-up resistors with the default of internal arbiter if the address pins are not connected to any other pci device. the pci block will drive the address pins if it is configured to be the pci arbiter?through por config pins?irrespective of whether it is disabled via the devdisr register or not. it may cause contention if there is any other pci device connected on the bus. 25. mdic0 is grounded through an 18.2- precision 1% resistor and mdic1 is connected gv dd through an 18.2- precision 1% resistor. these pins are used for automatic calibration of the ddr ios. 26. for sgmii mode. 27. connect to gnd. table 64. processor core clocking specifications characteristic maximum processor core frequency unit notes 667 mhz 800 mhz 1000 mhz 1067 mhz min max min max min max min max e500 core processor frequency 667 667 667 800 667 1000 667 1067 mhz 1, 2 notes : 1. caution: the ccb to sysclk ratio and e500 core to ccb ratio settings must be chosen such that the resulting sysclk frequency, e500 (core) frequency, and ccb frequency do not exceed their respective maximum or minimum operating frequencies. refer to section 19.2, ?ccb/sysclk pll ratio,? and section 19.3, ?e500 core pll ratio,? for ratio settings. 2. the minimum e500 core frequency is based on the minimum platform frequency of 333 mhz. table 63. mpc8544epinout listing (continued) signal package pin number pin type power supply notes
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 100 freescale semiconductor clocking 19.2 ccb/sysclk pll ratio the ccb clock is the clock that drives the e500 core complex bus (ccb), and is also called the platform clock. the frequency of the ccb is set using the following reset signals, as shown in table 66 : ? sysclk input signal ? binary value on la[28:31] at power up note that there is no default for this pll ratio; these signals must be pulled to the desired values. also note that the ddr data rate is the determining factor in selecting the ccb bus frequency, since the ccb frequency must equal the ddr data rate. table 65. memory bus clocking specifications characteristic maximum processor core frequency unit notes 667, 800, 1000, 1067 mhz min max memory bus clock speed 166 266 mhz 1, 2 notes: 1. caution: the ccb clock to sysclk ratio and e500 core to ccb clock ratio settings must be chosen such that the resulting sysclk frequency, e500 (core) frequency, and ccb clock frequency do not exceed their respective maximum or minimum operating frequencies. refer to section 19.2, ?ccb/sysclk pll ratio,? and section 19.3, ?e500 core pll ratio,? for ratio settings. 2. the memory bus speed is half of the ddr/ddr2 data rate, hence, half of the platform clock frequency. table 66. ccb clock ratio binary value of la[28:31] signals ccb:sysclk ratio binary value of la[28:31] signals ccb:sysclk ratio 0000 16:1 1000 8:1 0001 reserved 1001 9:1 0010 reserved 1010 10:1 0011 3:1 1011 reserved 0100 4:1 1100 12:1 0101 5:1 1101 reserved 0110 6:1 1110 reserved 0111 reserved 1111 reserved
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 freescale semiconductor 101 clocking 19.3 e500 core pll ratio table 67 describes the clock ratio between the e500 core complex bus (ccb) and the e500 core clock. this ratio is determined by the binary value of lbctl, lale, and lgpl2 at power up, as shown in table 67 . 19.4 pci clocks for specifications on the pci_clk, refer to the pci 2.2 local bus specifications . the use of pci_clk is optional if sysclk is in the range of 33?66 mhz. if sysclk is outside this range then use of pci_clk is required as a separate pci clock source, asynchronous with respect to sysclk. 19.5 security controller pll ratio table 67. e500 core to ccb clock ratio binary value of lbctl, lale, lgpl2 signals e500 core:ccb clock ratio binary value of lbctl, lale, lgpl2 signals e500 core:ccb clock ratio 000 4:1 100 2:1 001 reserved 101 5:2 010 reserved 110 3:1 011 3:2 111 7:2 table 68. sec frequency ratio signal name value (binary) ccb clk:sec clk lwe_b 0 2:1 1 13:1 2 notes: 1. in 2:1 mode the ccb frequency must be operating <= 400 mhz. 2. in 3:1 mode any valid ccb can be used. the 3:1 mode is the default ratio for security block.
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 102 freescale semiconductor clocking 19.6 frequency options 19.6.1 sysclk to platform frequency options table 69 shows the expected frequency values for the platform frequency when using a ccb clock to sysclk ratio in comparison to the memory bus clock speed. 19.6.2 platform to fifo restrictions please note the following fifo maximum speed restrictions based on platform speed. refer to section 4.4, ?platform to fifo restrictions,? for additional information. table 69. frequency options of sysclk with respect to memory bus speeds ccb to sysclk ratio sysclk (mhz) 33.33 41.66 66.66 83 100 111 133.33 platform /ccb frequency (mhz) 2 3 333 400 4 333 400 445 533 5 333 415 500 6 400 500 8 333 533 9 375 10 333 417 12 400 500 16 533 table 70. fifo maximum speed restrictions platform speed (mhz) maximum fifo speed for reference clocks tsec n _tx_clk, tsec n _rx_clk (mhz) 1 533 126 400 94 note: 1. fifo speed should be less than 24% of the platform speed.
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 freescale semiconductor 103 thermal 20 thermal this section describes the thermal specifications of the mpc8544e. 20.1 thermal characteristics table 71 provides the package thermal characteristics. table 72 provides the thermal resistance with heat sink in open flow. simulations with heat sinks were done with the package mounted on the 2s2p thermal test board. the thermal interface material was a typical thermal grease such as dow corning 340 or wakefield 120 grease. for system thermal modeling, the mpc8544e thermal model without a lid is shown in figure 60 . the table 71. package thermal characteristics characteristic jedec board symbol value unit notes junction-to-ambient natural convection single layer board (1s) r ja 26 c/w 1, 2 junction-to-ambient natural convection four layer board (2s2p) r ja 21 c/w 1, 2 junction-to-ambient (@200 ft/min) single layer board (1s) r ja 21 c/w 1, 2 junction-to-ambient (@200 ft/min) four layer board (2s2p) r ja 17 c/w 1, 2 junction-to-board thermal ? r jb 12 c/w 3 junction-to-case thermal ? r jc <0.1 c/w 4 notes: 1. junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, airflow, power dissipation of other components on the board, and board thermal resistance. 2. per jedec jesd51-2 and jesd51-6 with the board (jesd51-9) horizontal. 3. thermal resistance between the die and the printed-circuit board per jedec jesd51-8. board temperature is measured on the top surface of the board near the package. 4. thermal resistance between the active surface of the die and the case top surface determined by the cold plate method (mil spec-883 method 1012.1) with the calculated case temperature. actual thermal resistance is less than 0.1 c/w. table 72. thermal resistance with heat sink in open flow heat sink with thermal grease air flow thermal resistance ( c/w) wakefield 53 53 25 mm pin fin natural convection 6.1 wakefield 53 53 25 mm pin fin 1 m/s 3.0 aavid 35 31 23 mm pin fin natural convection 8.1 aavid 35 31 23 mm pin fin 1 m/s 4.3 aavid 30 30 9.4 mm pin fin natural convection 11.6 aavid 30 30 9.4 mm pin fin 1 m/s 6.7 aavid 43 41 16.5 mm pin fin natural convection 8.3 aavid 43 41 16.5 mm pin fin 1 m/s 4.3
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 104 freescale semiconductor thermal substrate is modeled as a block 29 29 1.18 mm with an in-plane conductivity of 18.0 w/m?k and a through-plane conductivity of 1.0 w/m?k. the solder balls and air are modeled as a single block 29 29 0.58 mm with an in-plane conductivity of 0.034 w/m?k and a through plane conductivity of 12.1 w/m?k. the die is modeled as 7.6 8.4 mm with a thickness of 0.75 mm. the bump/underfill layer is modeled as a collapsed thermal resistance betw een the die and substrate assuming a conductivity of 6.5 w/m?k in the thickness dimension of 0.07 mm. the die is centered on the substrate. the thermal model uses approximate dimensions to reduce grid. please refer to figure 59 for actual dimensions. 20.2 recommended thermal model table 73. mpc8544ethermal model conductivity value units die (7.6 8.4 0.75mm) silicon temperature dependent bump/underfill (7.6 8.4 0.070 mm) collapsed thermal resistance kz 6.5 w/m?k substrate (29 29 1.18 mm) kx 18 w/m?k ky 18 kz 1.0 solder and air (29 29 0.58 mm) kx 0.034 w/m?k ky 0.034 kz 12.1
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 freescale semiconductor 105 thermal figure 60. system level thermal model for mpc8544e (not to scale) the flotherm library files of the parts have a dense grid to accurately capture the laminar boundary layer for flow over the part in standard jedec environments, as well as the heat spreading in the board under the package. in a real system, however, the part will re quire a heat sink to be mounted on it. in this case, the predominant heat flow path will be from the die to the heat sink. grid density lower than currently in the package library file will suffice for these simulati ons. the user will need to determine the optimal grid for their specific case. 20.3 thermal management information this section provides thermal management information for the flip chip plastic ball grid array (fc-pbga) package for air-cooled applications. proper ther mal control design is pr imarily dependent on the system-level design?the heat sink, airflow, and th ermal interface material. the mpc8544e implements several features designed to assist with therma l management, including the temperature diode. the temperature diode allows an external device to monitor the die temperature in order to detect excessive temperature conditions and alert the system; see section 20.3.4, ?temperature diode,? for more information. subst rate die bump/underfill a a section a-a solder/air top view
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 106 freescale semiconductor thermal the recommended attachment method to the heat sink is illustrated in figure 61 . the heat sink should be attached to the printed-circuit board with the spring force centered over the die. this spring force should not exceed 10 pounds force (45 newton). figure 61. package exploded cross-sectional view with several heat sink options the system board designer can choose between several types of heat sinks to place on the device. there are several commercially-available heat sinks from the following vendors: aavid thermalloy 603-224-9988 80 commercial st. concord, nh 03301 internet: www.aavidthermalloy.com advanced thermal solutions 781-769-2800 89 access road #27. norwood, ma02062 internet: www.qats.com alpha novatech 408-567-8082 473 sapena ct. #12 santa clara, ca 95054 internet: www.alphanovatech.com international electronic research corporation (ierc) 818-842-7277 413 north moss st. burbank, ca 91502 internet: www.ctscorp.com millennium electronics (mei) 408-436-8770 loroco sites 671 east brokaw road san jose, ca 95112 internet: www.mei-thermal.com thermal interface material heat sink fc-pbga package heat sink clip printed-circuit board die adhesive or
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 freescale semiconductor 107 thermal tyco electronics 800-522-6752 chip coolers? p.o. box 3668 harrisburg, pa 17105-3668 internet: www.chipcoolers.com wakefield engineering 603-635-2800 33 bridge st. pelham, nh 03076 internet: www.wakefield.com ultimately, the final selection of an appropriate heat sink depends on many factors, such as thermal performance at a given air velocity , spatial volume, mass, attachment method, assembly, and cost. several heat sinks offered by aavid thermalloy, advanced thermal solutions, alpha novatech, ierc, chip coolers, millennium electronics, and wakefield engineering offer different heat sink-to-ambient thermal resistances, that will allow the mpc8544e to function in various environments. 20.3.1 internal package conduction resistance for the packaging technology, shown in table 71 , the intrinsic internal conduction thermal resistance paths are as follows: ? the die junction-to-case thermal resistance ? the die junction-to-board thermal resistance figure 62 depicts the primary heat transfer path for a pa ckage with an attached heat sink mounted to a printed-circuit board. figure 62. package with heat sink mounted to a printed-circuit board the heat sink removes most of the heat from the device. heat generated on the active side of the chip is conducted through the silicon and through th e heat sink attach material (or thermal interface material), and finally to the heat sink. the junction-to-case therma l resistance is low enough that the heat sink attach material and heat sink thermal resistance are the dominant terms. external resistance external resistance internal resistance radiation convection radiation convection heat sink printed-circuit board thermal interface material package/leads die junction die/package (note the internal versus external package resistance.)
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 108 freescale semiconductor thermal 20.3.2 thermal interface materials a thermal interface material is required at the package-to-heat sink interface to minimize the thermal contact resistance. for those applications where the heat sink is attached by spring clip mechanism, figure 63 shows the thermal performance of three thin-sheet thermal-interface materials (silicone, graphite/oil, floroether oil), a bare joint, and a join t with thermal grease as a function of contact pressure. as shown, the performance of these thermal interface materials improves with increasing contact pressure. the use of thermal grease significantly reduces the interface thermal resistance. the bare joint results in a thermal resistance approximately six times greater than the thermal grease joint. heat sinks are attached to the package by means of a spring clip to holes in the printed-circuit board (see figure 61 ). therefore, the synthetic grease offers the best thermal performance, especially at the low interface pressure. figure 63. thermal performance of select thermal interface materials the system board designer can choose between severa l types of thermal interface. there are several commercially-available thermal inte rfaces provided by the following vendors: chomerics, inc. 781-935-4850 77 dragon ct. woburn, ma 01801 internet: www.chomerics.com 0 0.5 1 1.5 2 0 1020304050607080 silicone sheet (0.006 in.) bare joint floroether oil sheet (0.007 in.) graphite/oil sheet (0.005 in.) synthetic grease contact pressure (psi) specific thermal resistance (k-in. 2 /w)
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 freescale semiconductor 109 thermal dow-corning corporation 800-248-2481 corporate center p.o.box 999 midland, mi 48686-0997 internet: www.dow.com shin-etsu microsi, inc. 888-642-7674 10028 s. 51st st. phoenix, az 85044 internet: www.microsi.com the bergquist company 800-347-4572 18930 west 78 th st. chanhassen, mn 55317 internet: www.bergquistcompany.com thermagon inc. 888-246-9050 4707 detroit ave. cleveland, oh 44102 internet: www.thermagon.com 20.3.3 heat sink selection examples the following section provides a heat sink selection ex ample using one of the commercially available heat sinks. for preliminary heat sink sizing, the die-junction temperature can be expressed as follows: t j = t i + t r + ( jc + int + sa ) p d where t j is the die-junction temperature t i is the inlet cabinet ambient temperature t r is the air temperature rise within the computer cabinet jc is the junction-to-case thermal resistance int is the adhesive or interface material thermal resistance sa is the heat sink base-to-ambient thermal resistance p d is the power dissipated by the device during operation the die-junction temperatures (t j ) should be maintained within the range specified in table 2 . the temperature of air cooling the component gr eatly depends on the ambient inlet air temperature and the air temperature rise within the electronic cabinet. an electronic cabinet inlet-air temperature (t i ) may range from 30 c to 40 c. the air temperature rise within a cabinet (t r ) may be in the range of 5 c to 10 c. the thermal resistance of the thermal interface material ( int ) may be about 1 c/w. assuming a t i of 30 c, a t r of 5 c, a fc-pbga package jc = 0.1, and a power consumption (p d ) of 5, the following expression for t j is obtained: die-junction temperature: t j = 30 c + 5 c + (0.1 c/w + 1.0 c/w + sa ) p d
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 110 freescale semiconductor thermal the heat sink-to-ambient thermal resistance ( sa ) versus airflow velocity for a thermalloy heat sink #2328b is shown in figure 64 . assuming an air velocity of 1 m/s, we have an effective sa+ of about 5 c/w, thus t j = 30 c + 5 c + (0.1 c/w + 1.0 c/w + 5 c/w) 5 resulting in a die-junction temperature of approximate ly 66, which is well within the maximum operating temperature of the component. figure 64. approach air velocity (m/s) 20.3.4 temperature diode the mpc8544e has a temperature diode on the microprocessor that can be used in conjunction with other system temperature monitoring devices (such as analog devices, adt7461?). these devices use the negative temperature coefficient of a diode operated at a constant current to determine the temperature of the microprocessor and its environment. for proper operation, the monitoring device used should auto-calibrate the device by canceling out the v be variation of each mpc8544e internal diode. the following are the specifications of the mpc8544e on-board temperature diode: v f > 0.40 v v f < 0.90 v operating range 2?300 a diode leakage < 10 na @ 125 c ideality factor over 5?150 a at 60 c: n = 1.085 0.2% 1 3 5 7 8 00.511.522.533.5 thermalloy #2328b pin-fin heat sink heat sink thermal resistance ( c/w) (25 28 15 mm) 2 4 6
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 freescale semiconductor 111 system design information ideality factor is defined as the de viation from the ideal diode equation: another useful equation is: where: i fw = forward current i s = saturation current v d = voltage at diode v f = voltage forward biased v h = diode voltage while i h is flowing v l = diode voltage while i l is flowing i h = larger diode bias current i l = smaller diode bias current q = charge of electron (1.6 10 ?19 c) n = ideality factor (normally 1.0) k = boltzman?s constant (1.38 10 ?23 joules/k) t = temperature (kelvins) the ratio of i h to i l is usually selected to be 10:1. the above simplifies to the following: v h ? v l = 1.986 10 ?4 nt solving for t, the equation becomes: 21 system design information this section provides electrical and thermal design recommendations for successful application of the mpc8544e. 21.1 system clocking this device includes six plls: ? the platform pll generates the platform clock from the externally supplied sysclk input. the frequency ratio between the platform and sysclk is selected using the platform pll ratio configuration bits as described in section 19.2, ?ccb/sysclk pll ratio.? i fw = i s e qv f nkt ? 1 i h i l v h ? v l = n ln kt q v h ? v l 1.986 10 ?4 nt =
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 112 freescale semiconductor system design information ? the e500 core pll generates the core clock as a slave to the platform clock. the frequency ratio between the e500 core clock and the platform clock is selected using the e500 pll ratio configuration bits as described in section 19.3, ?e500 core pll ratio.? ? the pci pll generates the clocking for the pci bus. ? the local bus pll generates the clock for the local bus. ? there are two plls for the serdes block. 21.2 power supply design and sequencing 21.2.1 pll power supply filtering each of the plls listed above is provided w ith power through independent power supply pins (av dd _plat, av dd _core, av dd _pci, av dd _lbiu, and av dd _srds, respectively). the av dd level should always be equivalent to v dd , and preferably these voltages will be derived directly from v dd through a low frequency filter scheme such as the following. there are a number of ways to reliably provide power to the plls, but the recommended solution is to provide independent filter circuits pe r pll power supply as illustrated in figure 65 , one to each of the av dd pins. by providing independent filters to each pll the opportunity to cause noise injection from one pll to the other is reduced. this circuit is intended to filter noise in the p lls resonant frequency range from a 500 khz to 10 mhz range. it should be built with surface mount capacitor s with minimum effective series inductance (esl). consistent with the recommendations of dr. howard johnson in high speed digital design: a handbook of black magic (prentice hall, 1993), multiple small capacito rs of equal value are recommended over a single large value capacitor. each circuit should be placed as cl ose as possible to the specific av dd pin being supplied to minimize noise coupled from nearby circuits. it should be possible to route directly from the capacitors to the av dd pin, which is on the periphery of 783 fc-pbga the footprint, without the inductance of vias. figure 65 shows the pll power supply filter circuit. figure 65. mpc8544e pll power supply filter circuit the av dd _srds n signals provide power for the analog portions of the serdes pll. to ensure stability of the internal clock, the power supplied to the pll is filtered using a circuit similar to the one shown in figure 66 . for maximum effectiveness, the filter circu it is placed as closely as possible to the av dd _srds n balls to ensure it filters out as much noise as possible. the ground connection should be near the av dd _srds n balls. the 0.003-f capacitor is closest to the balls, followed by the 1-f capacitor, and finally the 1- resistor to the board supply plane. the capacitors are connected from v dd av dd 2.2 f 2.2 f gnd low esl surface mount capacitors 10
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 freescale semiconductor 113 system design information av dd _srds n to the ground plane. use ceramic chip capacitors with the highest possible self-resonant frequency. all traces should be kept short, wide, and direct. figure 66. serdes pll power supply filter circuit note the following: ?av dd_ srds should be a filtered version of sv dd . ? signals on the serdes interface are fed from the xv dd power plane. 21.3 decoupling recommendations due to large address and data buses, and high operati ng frequencies, the device can generate transient power surges and high frequency noise in its power suppl y, especially while driving large capacitive loads. this noise must be prevented from reaching other components in the mpc8544e system, and the device itself requires a clean, tightly regulated source of power. therefore, it is recommended that the system designer place at least one decoupling capacitor at each v dd , tv dd , bv dd , ov dd , gv dd , and lv dd pin of the device. these decoupling capacitors should receive their power from separate v dd , tv dd , bv dd , ov dd , gv dd , and lv dd ; and gnd power planes in the pcb, utilizing short traces to minimize inductance. capacitors may be placed directly under th e device using a standard escape pattern. others may surround the part. these capacitors should have a value of 0.01 or 0.1 f. only ceramic smt (surface mount technology) capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes. in addition, it is recommended that there be several bulk storage capacitors distributed around the pcb, feeding the v dd , tv dd , bv dd , ov dd , gv dd , and lv dd planes, to enable quick recharging of the smaller chip capacitors. these bulk capacitors should ha ve a low esr (equivalent series resistance) rating to ensure the quick response time necessary. they should also be connected to the power and ground planes through two vias to minimize inductance. suggested bulk capacitors?100?330 f (avx tps tantalum or sanyo oscon). however, customers should work directly with their power regulator vendor for best values and types of bulk capacitors. 21.4 serdes block power supply decoupling recommendations the serdes block requires a clean, tightly regulated source of power (sv dd and xv dd ) to ensure low jitter on transmit and reliable recovery of data in the receiver. an appropriate decoupling scheme is outlined below. 2.2 f 1 0.003 f gnd 1.0 av dd _srds note: 1. an 0805 sized capacitor is recommended for system initial bring-up. sv dd 2.2 f 1
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 114 freescale semiconductor system design information only surface mount technology (smt) capacitors shoul d be used to minimize inductance. connections from all capacitors to power and ground should be done with multiple vias to further reduce inductance. ? first, the board should have at least 10 10-nf smt ceramic chip capacitors as close as possible to the supply balls of the device. where the board has blind vias, these capacitors should be placed directly below the chip supply and ground connecti ons. where the board does not have blind vias, these capacitors should be placed in a ring around the device as close to the supply and ground connections as possible. ? second, there should be a 1-f ceramic chip capac itor on each side of the device. this should be done for all serdes supplies. ? third, between the device and any serdes voltage regulator there should be a 10-f, low equivalent series resistance (esr) smt tantalum chip capacitor and a 100-f, low esr smt tantalum chip capacitor. this shoul d be done for all serdes supplies. 21.5 connection recommendations to ensure reliable operation, it is highly recommende d to connect unused inputs to an appropriate signal level. all unused active low inputs should be tied to v dd , tv dd , bv dd , ov dd , gv dd , and lv dd as required. all unused active high inputs should be conne cted to gnd. all nc (no connect) signals must remain unconnected. power and ground connecti ons must be made to all external v dd , tv dd , bv dd , ov dd , gv dd , and lv dd ; and gnd pins of the device. 21.6 pull-up and pull-down resistor requirements the mpc8544e requires weak pull-up resistors (2?10 k is recommended) on open drain type pins including i 2 c pins and mpic interrupt pins. correct operation of the jtag interface requires configuration of a group of system control pins as demonstrated in figure 69 . care must be taken to ensure that these pins are maintained at a valid deasserted state under normal operating conditions as most have asynchronous behavior and spurious assertion will give unpredictable results. the following pins must not be pulled down during power-on reset: tsec3_txd[3], hreset_req , trig_out/ready/quiesce , msrcid[2:4], asleep. the dma_dack[0:1] and test_sel pins must be set to a proper state during por configuration. refer to the pinout listing table ( table 63 ) for more details. refer to the pci 2.2 local bus specifications, for all pullups required for pci. 21.7 output buffer dc impedance the mpc8544e drivers are characterized over process, voltage, and temperature. for all buses, the driver is a push-pull single-ended driver type (open drain for i 2 c). to measure z 0 for the single-ended drivers, an external resistor is connected from the chip pad to ov dd or gnd. then, the value of each resistor is varied until the pad voltage is ov dd /2 (see figure 67 ). the output impedance is the average of two components, the resistances of the pull-up and pull-down devices. when data is held high, sw1 is closed (sw2 is open) and r p is trimmed until the voltage at the pad equals ov dd /2. r p then becomes the resistance of the pull-up devices. r p and r n are designed to be close to each other in value. then, z 0 =(r p +r n )/2.
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 freescale semiconductor 115 system design information figure 67. driver impedance measurement table 74 summarizes the signal impedance targets. the driver impedances are targeted at minimum v dd , nominal ov dd , 90 c. 21.8 configuration pin muxing the mpc8544eprovides the user with power-on configuration options which can be set through the use of external pull-up or pull-down resistors of 4.7 k on certain output pins (see customer visible configuration pins). these pins are generally used as output only pins in normal operation. while hreset is asserted however, these pins are treated as inputs. the value presented on these pins while hreset is asserted, is latched when hreset deasserts, at which time the input receiver is disabled and the i/o circuit takes on its normal function. most of these sampled configuration pins are equipped with an on-chip gated resistor of approximately 20 k . this value should permit the 4.7-k resistor to pull the configuration pin to a valid logic low level. the pull-up resistor is enabled only during hreset (and for platform /system clocks after hreset deassertion to ensure capture of the reset value). when the input receiver is disabled the pull-up is also, thus allowi ng functional operation of the pin as an output with minimal signal quality or delay disruption. the default va lue for all configuration bits treated this way has been encoded such that a high voltage level puts the de vice into the default state and external resistors are needed only when non-default settings are required by the user. table 74. impedance characteristics impedance local bus, ethernet, duart, control, configuration, power management pci ddr dram symbol unit r n 43 target 25 target 20 target z 0 w r p 43 target 25 target 20 target z 0 w note: nominal supply voltages. see ta b l e 1 . ov dd ognd r p r n pad data sw1 sw2
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 116 freescale semiconductor system design information careful board layout with stubless connections to th ese pull-down resistors coupled with the large value of the pull-down resistor should minimize the disruption of signal quality or speed for output pins thus configured. the platform pll ratio and e500 pll ratio configura tion pins are not equipped with these default pull-up devices. 21.9 jtag configuration signals correct operation of the jtag interface requires configuration of a group of system control pins as demonstrated in figure 69 . care must be taken to ensure that these pins are maintained at a valid deasserted state under normal operating conditions as most have asynchronous behavior and spurious assertion will give unpredictable results. boundary-scan testing is enabled through the jtag interface signals. the trst signal is optional in the ieee std. 1149.1 specification, but is provided on all processors built on power architecture? technology. the device requires trst to be asserted during reset conditions to ensure the jtag boundary logic does not interfere with normal chip operation. while it is possible to force the tap controller to the reset state using only the tck and tms signals, generally systems will assert trst during the power-on reset flow. simply tying trst to hreset is not practical because the jtag interface is also used for accessing the common on-chip processor (cop) function. the cop function of these processors allow a remote computer system (typically, a pc with dedicated hardware and debugging software) to access and control the internal operations of the processor. the cop interface connects primarily through the jtag port of the processor, with some additional status monitoring signals. the cop port requires the ability to independently assert hreset or trst in order to fully control the processor. if the target system ha s independent reset sources, such as voltage monitors, watchdog timers, power supply failures, or push-button switches, then the cop reset signals must be merged into these signals with logic. the arrangement shown in figure 69 allows the cop port to independently assert hreset or trst , while ensuring that the target can drive hreset as well. the cop interface has a standard header, shown in figure 68 , for connection to the target system, and is based on the 0.025" square-post, 0.100" centered header assembly (often called a berg header). the connector typically has pin 14 removed as a connector key. the cop header adds many benefits such as breakpoints, watchpoints, register and memory examination/modification, and othe r standard debugger features. an inexpensive option can be to leave the cop header unpopulated until needed. there is no standardized way to number the cop head er; consequently, many diff erent pin numbers have been observed from emulator vendors. some are numbe red top-to-bottom then left-to-right, while others use left-to-right then top-to-bottom, while still othe rs number the pins counter clockwise from pin 1 (as with an ic). regardless of the numbering, the signal placement recommended in figure 68 is common to all known emulators.
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 freescale semiconductor 117 system design information 21.9.1 termination of unused signals if the jtag interface and cop header will not be used, freescale recommends the following connections: ?trst should be tied to hreset through a 0-k isolation resistor so that it is asserted when the system reset signal (hreset ) is asserted, ensuring that the jtag scan chain is initialized during the power-on reset flow. freescale recommends that the cop header be designed into the system as shown in figure 69 . if this is not possible, the isolation resistor will allow future access to trst in case a jtag interface may need to be wired onto the system in future debug situations. ? no pull-up/pull-down is required for tdi, tms, or tdo. figure 68. cop connector physical pinout 3 13 9 5 1 6 10 15 11 7 16 12 8 4 key no pin 1 2 cop_tdo cop_tdi cop_run/stop nc cop_trst cop_vdd_sense cop_chkstp_in nc nc gnd cop_tck cop_tms cop_sreset cop_hreset cop_chkstp_out
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 118 freescale semiconductor system design information figure 69. jtag interface connection hreset from target board sources cop_hreset 13 cop_sreset sreset nc 11 cop_vdd_sense 2 6 5 15 10 10 k 10 k cop_chkstp_in ckstp_in 8 cop_tms cop_tdo cop_tdi cop_tck tms tdo tdi 9 1 3 4 cop_trst 7 16 2 10 12 (if any) cop header 14 3 notes: 3. the key location (pin 14) is not physically present on the cop header. 10 k trst 1 10 k 10 k 10 k ckstp_out cop_chkstp_out 3 13 9 5 1 6 10 15 11 7 16 12 8 4 key no pin cop connector physical pinout 1 2 nc sreset 2. populate this with a 10- resistor for short-circuit/current-limiting protection. nc ov dd 10 k hreset 1 in order to fully control the processor as shown here. 4. although pin 12 is defined as a no connect, some debug tools may use pin 12 as an additional gnd pin for 1. the cop port and target board should be able to independently assert hreset and trst to the processor improved signal integrity. tck 4 5 5. this switch is included as a precaution for bsdl testing. the switch should be closed to position a during bsdl testing to avoid accidentally asserting the trst line. if bsdl testing is not being performed, this switch should be 10 k 6 6. asserting sreset causes a machine check interrupt to the e500 core. a b closed to position b. 10 k
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 freescale semiconductor 119 system design information 21.10 guidelines for high-speed interface termination 21.10.1 serdes interface entirely unused if the high-speed serdes interface is not used at all, the unused pin should be terminated as described in this section. however, the serdes must al ways have power applied to its supply pins. the following pins must be left unconnected (float): ?sd_tx[0:7] ?sd_tx [0:7] the following pins must be connected to gnd: ?sd_rx[0:7] ?sd_rx [0:7] ?sd_ref_clk ?sd_ref_clk 21.10.2 serdes interface partly unused if only part of the high speed serdes interface pins are used, the remaining high-speed serial i/o pins should be terminated as described in this section. the following pins must be left unconnected (float) if not used: ?sd_tx[0:7] ?sd_tx [0:7] the following pins must be connected to gnd if not used: ?sd_rx[0:7] ?sd_rx [0:7] ?sd_ref_clk ?sd_ref_clk 21.11 guideline for pci interface termination pci termination if not used at all. option 1 ? if pci arbiter is enabled during por, ? all ad pins will be driven to the stable states after por. therefore, all ads pins can be floating. ? all pci control pins can be grouped together and tied to ov dd through a single 10-k resistor. ? it is optional to disable pci block through devdisr register after por reset. option 2 ? if pci arbiter is disabled during por,
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 120 freescale semiconductor device nomenclature ? all ad pins will be in the input state. therefore, all ads pins need to be grouped together and tied to ov dd through a single (or multiple) 10-k resistor(s). ? all pci control pins can be grouped together and tied to ov dd through a single 10-k resistor. 21.12 guideline for lbiu termination if the lbiu parity pins are not used. here is the termination recommendation: ? for ldp[0:3]: tie them to ground or the power supply rail via a 4.7-k resistor. ? for lpbse: tie it to the power supply rail via a 4.7-k resistor (pull-up resistor). 22 device nomenclature ordering information for the parts fully covered by th is hardware specifications document is provided in section 22.3, ?part marking.? contact your local freescale sales office or regional marketing team for order information. 22.1 industrial and commercial tier qualification the mpc8544e device has been tested to meet the commercial tier qualification. table 75 provides a description for commercial a nd industrial qualifications. table 75. commercial and industrial description tier 1 typical application use time power-on hours example of typical applications commercial 5 years part-time/ full-time pc's, consumer electronics, office automation, soho networking, portable telecom products, pda's, etc. industrial 10 years typically full-time installed telecom equipment, work stations, servers, warehouse equipment, etc. note: 1. please refer to ta b l e 2 for operating temperature ranges. temperature is independent of tier and will vary per product.
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 freescale semiconductor 121 device nomenclature 22.2 nomenclature of parts fully addressed by this document table 76 provides the freescale part numbering nomenclature for the mpc8544e. table 76. device nomenclature mpc nnnn e c hx aa x b produc t code part identifier encryption acceleration temperature range package 1 processor frequency 2 platform frequency revision level mpc 8544 blank = not included e = included a = commercial tier standard temp range(0 to 105 c) b or blank = industrial tier standard temp range(0 to 105 c) c = industrial tier extended temp range(?40 to 105 c) d = commercial tier extended temp range(?40 to 105 c) vt = fc-pbga (lead free) al = 667 mhz an = 800 mhz aq = 1000 mhz ar = 1067 mhz f = 333 mhz g = 400 mhz j = 533 mhz contact local freescale sales office notes: 1. see section 18, ?package description,? for more information on available package types. 2. processor core frequencies supported by parts addressed by this specification only. not all parts described in this specification support all core frequencies. additionally, parts addressed by part number specifications may support other maximum core frequencies.
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 122 freescale semiconductor device nomenclature 22.3 part marking parts are marked as in the example shown in figure 70 . figure 70. part marking for fc-pbga device 22.4 part numbering table 77 lists all part numbers that are offered for mpc8544e. table 77. mpc8544e part numbers part number core frequency (mhz) platform frequency (mhz) mpc8544eavtalf 667 333 mpc8544edvtalf 667 333 mpc8544eavtang 800 400 mpc8544edvtang 800 400 mpc8544eavtaqg 1000 400 mpc8544eavtarj 1067 533 mmmmm ccccc atwlyyww notes : ccccc is the country of assembly. this space is left blank if parts are assembled in the united states. mmmmm is the 5-digit mask number. atwlyyww is the traceability code. fc-pbga mpcnnnnchxaaxb
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 freescale semiconductor 123 device nomenclature table 78 lists all part numbers that are offered for mpc8544. table 78. mpc8544 part numbers part number core frequency (mhz) platform frequency (mhz) MPC8544AVTALF 667 333 mpc8544dvtalf 667 333 mpc8544avtang 800 400 mpc8544dvtang 800 400 mpc8544avtaqg 1000 400 mpc8544avtarj 1067 533
mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 124 freescale semiconductor document revision history 23 document revision history table 79 provides a revision history for the mpc8544e hardware specification. table 79. mpc8544e document revision history revision date substantive change(s) 0 04/2008 initial release. 1 6/2008 correction in ta b l e 1 9 ddr sdram output ac timing specifications tmck max value improvement to section 16, ?high-speed serial interfaces (hssi) update figure 59 mechanical dimensions correction in ta b l e 4 9 local bus general timing parameters?pll bypassed
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mpc8544e powerquicc? iii integrated processor hardware specifications, rev. 1 126 freescale semiconductor document revision history this page intentionally left blank
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document number: mpc8544eec rev. 1 06/2008 information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters which may be provided in freescale semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 +1-800 441-2447 or +1-303-675-2140 fax: +1-303-675-2150 ldcforfreescalesemiconductor @hibbertgroup.com freescale are trademarks or registered trademarks of freescale semiconductor, inc. in the u.s. and other countries. all other product or service names are the property of their respective owners. the power architecture and power.org word marks and the power and power.org logos and related marks are trademarks and service marks licensed by power.org. ieee 802.1, 802.3, 802.3ab, 802.3ac, 802.3u, 802.3x, 802.3z, and 1149.1 are registered trademarks of the institute of electrical and electronics engineers, inc. (ieee). this product is not endorsed or approved by the ieee. ? freescale semiconductor, inc., 2008. all rights reserved.

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